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AMD M56 Reference Manual

AMD M56 Reference Manual

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M56
Register Reference Guide
Technical Reference Manual
Rev 0.03o
P/N: RRG-216M56-03oOEM
© 2007 Advanced Micro Devices, Inc.

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  • Page 1 Register Reference Guide Technical Reference Manual Rev 0.03o P/N: RRG-216M56-03oOEM © 2007 Advanced Micro Devices, Inc.
  • Page 2 AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur.

  • Page 3: Table Of Contents

    Secondary Display Video Overlay Gamma Correction Registers ................2-242 2.7.16 Secondary Display Graphics and Overlay Blending Registers .................2-246 2.7.17 Secondary Display Color Matrix Transform Registers ....................2-250 2.7.18 Secondary Display Subsampling Registers ........................2-254 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary TOC-1...
  • Page 4 A.17 VGA GRPH Registers Sorted By Name ............................. A-61 A.18 VGA SEQ Registers Sorted By Name ............................A-62 A.19 All Registers Sorted by Name ............................... A-63 Appendix B: Revision History M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. TOC-2 Proprietary...

  • Page 5: About This Manual

    Chapter 1 Introduction About this Manual This manual serves as a register reference guide to the M56 graphics controller. • Chapter 1 outlines the notations and conventions used throughout this manual. • Chapter 2 provides a detailed description of the registers.
  • Page 6 [aperName:offset] - single mapping, to one aperture/decode and one offset [aperName1, aperName2, …, aperNameN:offset] - multiple mappings to different apertures/decodes but same offset [aperName:startOffset-endOffset] - mapped to an offset range in the same aperture/decode M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 7 “Clock Generator Registers” on page 2-155 “VGA Registers” on page 2-165 “Display Controller Registers” on page 2-198 “CRTC Registers” on page 2-267 “Display Output Registers” on page 2-295 “LVDS Registers” on page 2-340 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...

  • Page 8: Memory Controller Registers

    MEM_PWRUP_COMPL (R) 0=SDRAM Init in Process 1=Ready MC_IDLE (R) Indicates that there are no pending or in-process requests in the MC 0=Not Idle 1=Idle Status register for memory controller M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 9 This register defines the location of the frame buffer in the internal address space. The internal address space has 32 address bits. Minimum Frame buffer size for M56 is 16 MB, and the start location is required to be on a 16 MB boundary. Therefore START(23:0) must be 0x000000 and TOP(23:0) must be 0xFFFFFF.
  • Page 10 10=Bit 17 11=Bit 18 12=Bit 19 13=Bit 20 14=Bit 21 15=Bit 22 16=Bit 23 17=Bit 24 18=Bit 25 19=Bit 26 20=Bit 27 21=Bit 28 22=Bit 29 23=Bit 30 24=Bit 31 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 11 17=Bit 24 18=Bit 25 19=Bit 26 20=Bit 27 21=Bit 28 22=Bit 29 23=Bit 30 24=Bit 31 MC_CHANNEL_SIZE 64-bit per channel (not supported by M56 sequencer) 0=32-bit per channel 1=64-bit per channel MEM_NUM_CHANNELS 25:24 0=One channel 1=Two channels 2=Four channels 3=Reserved...
  • Page 12 10=Bit 17 11=Bit 18 12=Bit 19 13=Bit 20 14=Bit 21 15=Bit 22 16=Bit 23 17=Bit 24 18=Bit 25 19=Bit 26 20=Bit 27 21=Bit 28 22=Bit 29 23=Bit 30 24=Bit 31 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 13 1=MC bist enabled MC_RST_CTRL 0=MC soft-reset passthru 1=MC soft-reset force ENABLE_PAGE_TABLES 0=disable page tables to dram interface 1=enable page tables to dram interface Basic DRAM configuration and rank/bank address mapping. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...
  • Page 14 In HCLK units. Using DRAM timing parameters. MC_ARB_DRAM_PENALTIES2 - RW - 32 bits - MCIND:0x14 Field Name Bits Default Description MC_SHORT_TO_COVER_PENALTY ~ 1/2 MC_ACTIVATION_PENALTY MC_READ_ACTIVATION 13:8 tRAR MC_WRITE_ACTIVATION 21:16 tRAW MC_PRECHARGE 29:24 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 15 1=Age CB write requests MC_ZBW_AGEDIV 12:8 MC_ZBW_USEAGE 0=Do not age ZB write requests 1=Age ZB write requests MC_MCIF_AGEDIV 20:16 MC_MCIF_USEAGE 0=Do not age MCIF write requests 1=Age MCIF write requests © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...
  • Page 16 STB_CNT 11:8 DRAM standby counter. Number of idle cycles before dynamic CKE is enabled. This prevents the CKE from turning off too easily. CKE_DYN Dynamic CKE. 0=Disable 1=Enable M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-10 Proprietary...
  • Page 17 Read to read time - 1 (different rank). TW2R 20:16 Write to read turn around time - 1. 28:24 CAS to data return latency - 2 (0 to 20). CAS related parameters in hclk cycles. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-11...
  • Page 18 Creates an extra strobe in the preamble of a burst. This is needed if DQS is default high and its falling edge is used as a trigger. 0=No read pre strobe 1=Extra read pre strobe M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-12 Proprietary...
  • Page 19 6=DQS receive enable extended by 6 cycles 7=DQS receive enable extended by 7 cycles 8=DQS receive enable always on RST_SEL 0=Reset pointers off 1=Reset pointers on 2=Reset pointers before read 3=Reset pointers during refresh © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-13...
  • Page 20 Extends on-die-termination enable after data burst. 0=ODT not extended 1=ODT extended by one cycle Channel 0's write command parameters in hclk. MC_SEQ_WR_CTL_I1 - RW - 32 bits - MCIND:0x67 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-14 Proprietary...
  • Page 21 Turns off address and command manually. 0=Normal 1=Tristate CKE_BIT Bypass value for clock enable. CKE_SEL Selects clock enable bypass value. 0=Normal CKE 1=Set CKE bit Channel 1's misc. control parameters. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-15...
  • Page 22 Channel 1's clock pad control parameters. MC_SEQ_CMD_PAD_CNTL_I0 - RW - 32 bits - MCIND:0x6E Field Name Bits Default Description NMOS_PD NMOS pulldown value. PSTR_OFF P drive strength/offset. NSTR_OFF 11:8 N drive strength/offset. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-16 Proprietary...
  • Page 23 Channel 1's data pad control parameters. MC_SEQ_QS_PAD_CNTL_I0 - RW - 32 bits - MCIND:0x72 Field Name Bits Default Description NMOS_PD NMOS pulldown value. PSTR_OFF P drive strength/offset. NSTR_OFF 11:8 N drive strength/offset. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-17...
  • Page 24 MC_SEQ_CMD - RW - 32 bits - MCIND:0x76 Field Name Bits Default Description 15:0 This field is mapped directly to the address bus. Note: Previous write data is not stored. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-18 Proprietary...
  • Page 25 1=Clk out on YCLK fall, 1/4 clock delay MEM_FALL_OUT_CMD Advance 1/2 yclk in command bits 0=Command out on YCLK rise 1=Command out on YCLK fall, 1/4 clock delay © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-19...
  • Page 26 1=Clk out on YCLK fall, 1/4 clock delay MEM_FALL_OUT_CMD Advance 1/2 yclk in command bits 0=Command out on YCLK rise 1=Command out on YCLK fall, 1/4 clock delay M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-20 Proprietary...
  • Page 27 MC_IO_RD_DQ_CNTL_I0 - RW - 32 bits - MCIND:0x84 Field Name Bits Default Description MADJ0 Byte 0 MADJ1 15:8 Byte 1 MADJ2 23:16 Byte 2 MADJ3 31:24 Byte 3 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-21...
  • Page 28 MC_IO_WR_CNTL_I0 - RW - 32 bits - MCIND:0x88 Field Name Bits Default Description CK_DLY Clock delay CMD_DLY Command delay ADR_DLY 14:10 Address delay Channel 0's delay line parameters clock/command/address bits M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-22 Proprietary...
  • Page 29 NPL Termination control P side NTERM NPL Termination control N side PDRV 11:8 NPL Drive control P side NDRV 15:12 NPL Drive control N side RECV_DUTY 17:16 Pad Receive Duty control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-23...
  • Page 30 NPL Termination control N side PDRV 11:8 NPL Drive control P side NDRV 15:12 NPL Drive control N side RECV_DUTY 17:16 Pad Receive Duty control DRV_DUTY 19:18 Pad Drive Duty control M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-24 Proprietary...
  • Page 31 NPL Drive control N side RECV_DUTY 17:16 Pad Receive Duty control DRV_DUTY 19:18 Pad Drive Duty control PREAMP 21:20 NPL Pre-emphasis enable select, [1:0] for finger [7:6], 0=>disable, 1=>enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-25...
  • Page 32 Default Description DLY0 Byte 3 DLY1 Byte 2 DLY2 14:10 Byte 1 DLY3 19:15 Byte 0 Channel 0's delay line parameters strobe bits. NOTE: Byte orders are swapped!!! M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-26 Proprietary...
  • Page 33 PDELAY Current Delay on CLKP NDELAY Current Delay on CLKN PEARLY Current CLKP is early than CLKN NEARLY Current CLKN is early than CLKP Channel 1's NPL status. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-27...
  • Page 34 IMP_N_MEM_DQ_SN_I0 (R) N drive strength of sequencer 0 data byte 0. IMP_P_MEM_DQ_SP_I0 (R) IMP_N_MEM_DQ_SN_I1 (R) 11:8 N drive strength of sequencer 1 data byte 0. IMP_P_MEM_DQ_SP_I1 (R) 15:12 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-28 Proprietary...
  • Page 35 Selects flow control signals from node 3 in clockwise route. 0=Group 0 1=Group 1 2=Group 2 3=Block CKW4 19:18 Selects flow control signals from node 4 in clockwise route. 0=Group 0 1=Group 1 2=Group 2 3=Block © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-29...
  • Page 36 Read data inversion control. 0=Disable read data inversion 1=Enable read data inversion MSK_DF1 Data inversion mask polarity. 0=Inverse mask active low 1=Inverse mask active high Misc. RBS control register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-30 Proprietary...
  • Page 37 MC_MISC_1 - RW - 32 bits - MCIND:0xF1 Field Name Bits Default Description MISC1 31:0 32-bit storage. Dummy register for temporary storage. MC_DEBUG - RW - 32 bits - MCIND:0xFE Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-31...
  • Page 38 0=normal operation 1=clear CLEAR_PROTECTION_FAULT_STATUS write 1 to clear fault status which occurs on rising edge 0=normal operation 1=clear EFFECTIVE_L2_QUEUE_SIZE 24:21 (3...7) 2**(field) latency compensation queue entries ENABLE_SURFACE_PROBE_FLOW_CONTRO 0=off 1=on M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-32 Proprietary...
  • Page 39 ENABLE_PRIVILEGED_MODE 0=off 1=on This register provides control for Context 2 in Page Table Unit 0. MC_PT0_CONTEXT3_CNTL - RW - 32 bits - MCIND:0x105 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-33...
  • Page 40 0=off 1=on PAGE_TABLE_TYPE 0=flat 1=multi-level ENABLE_PRIVILEGED_MODE 0=off 1=on This register provides control for Context 6 in Page Table Unit 0. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-34 Proprietary...
  • Page 41 This register initiates a surface probe sequence in Page Table Unit 0. The page address must be on a 4K-byte boundary. If handling of surface probes is not enabled, they are reported as always passing. Although both PT units contain this register, only PT0 can process surface probes. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-35...
  • Page 42 This register defines the physical page address used for ignored protection faults while reading in Page Table Unit 0 Context 1. The page address must be on a 4K-byte boundary. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
  • Page 43 This register defines the physical base address of the flat page table for Context 0 in Page Table Unit 0. The page address must be on a 4K-byte boundary. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-37...
  • Page 44 This register defines the physical base address of the flat page table for Context 6 in Page Table Unit 0. The page address must be on a 4K-byte boundary. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-38...
  • Page 45 2M-byte boundary. The mapping range is inclusive between starting and ending addresses. If the ending address is less than the starting address, all mappings will be invalid. MC_PT0_CONTEXT5_FLAT_START_ADDR - RW - 32 bits - MCIND:0x141 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-39...
  • Page 46 MC_PT0_CONTEXT3_FLAT_END_ADDR - RW - 32 bits - MCIND:0x14F Field Name Bits Default Description LOGICAL_END_ADDR 31:0 0x1fffff NOTE: Bits 0:20 of this field are hardwired to ONE. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-40 Proprietary...
  • Page 47 This register defines the physical base address of the multi-level page table for Context 1 in Page Table Unit 0. This physical address must begin on a 4K-byte boundary. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-41...
  • Page 48 MC_PT0_CLIENT0_CNTL - RW - 32 bits - MCIND:0x16C Field Name Bits Default Description ENABLE_TRANSLATION_MODE_OVERRIDE can override translation mode requested by memory client at pt/l1 interface 0=no (obey client request) 1=yes (override client request) M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-42 Proprietary...
  • Page 49 0. other than system context, these assignments are suggestions only -- the driver will determine actual assignments. 0=system 1=gpu 2=host 3=idct © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-43...
  • Page 50 0=always physical access 1=always logical access via system context 0 page table 2=inside system aperture is mapped, outside is unmapped 3=inside system aperture is unmapped, outside is mapped M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-44 Proprietary...
  • Page 51 EFFECTIVE_L1_CACHE_SIZE 13:11 (0...4) 2**(field) page table entries ENABLE_FRAGMENT_PROCESSING 0=off 1=on EFFECTIVE_L1_QUEUE_SIZE 17:15 (0...4) 2**(field) latency compensation queue entries ENABLE_PROTECTION_FAULTS enable/disable protection fault processing for this client 0=disable 1=enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-45...
  • Page 52 This register provides static control for Client 4 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table Unit will service roughly 17 clients. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
  • Page 53 0=no (obey client request) 1=yes (override client request) TRANSLATION_MODE_OVERRIDE l1 client will follow system access mode when translation is off 0=always translate off 1=always translate on © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-47...
  • Page 54 This register provides static control for Client 6 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table Unit will service roughly 17 clients. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
  • Page 55 0=no (obey client request) 1=yes (override client request) TRANSLATION_MODE_OVERRIDE l1 client will follow system access mode when translation is off 0=always translate off 1=always translate on © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-49...
  • Page 56 0. other than system context, these assignments are suggestions only -- the driver will determine actual assignments. 0=system 1=gpu 2=host 3=idct M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-50 Proprietary...
  • Page 57 0=always physical access 1=always logical access via system context 0 page table 2=inside system aperture is mapped, outside is unmapped 3=inside system aperture is unmapped, outside is mapped © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-51...
  • Page 58 EFFECTIVE_L1_CACHE_SIZE 13:11 (0...4) 2**(field) page table entries ENABLE_FRAGMENT_PROCESSING 0=off 1=on EFFECTIVE_L1_QUEUE_SIZE 17:15 (0...4) 2**(field) latency compensation queue entries ENABLE_PROTECTION_FAULTS enable/disable protection fault processing for this client 0=disable 1=enable M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-52 Proprietary...
  • Page 59 This register provides static control for Client 12 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table Unit will service roughly 17 clients. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-53...
  • Page 60 This register provides static control for Client 13 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table Unit will service roughly 17 clients. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
  • Page 61 0=no (obey client request) 1=yes (override client request) TRANSLATION_MODE_OVERRIDE l1 client will follow system access mode when translation is off 0=always translate off 1=always translate on © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-55...
  • Page 62 0. other than system context, these assignments are suggestions only -- the driver will determine actual assignments. 0=system 1=gpu 2=host 3=idct M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-56 Proprietary...
  • Page 63 This register provides static control for Client 16 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table Unit will service roughly 17 clients. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-57...

  • Page 64: Bus Interface Registers

    If the power state is D1-D3, then MEM access is disabled. This bit, if set to 1, will disabled this behaviour. Meaning, it will enabled MEM access. 0=Normal 1=Disable M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-58 Proprietary...
  • Page 65 CONFIG_APER_0_BASE - R - 32 bits - HIDEC:0x100 Field Name Bits Default Description APER_0_BASE 31:0 Aperture 0 Base NOTE: Bits 0:24 of this field are hardwired to ZERO. Configuration Aperture 0 Base Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-59...
  • Page 66 VENDOR_ID - R - 16 bits - [CFGF0_DEC:0x0] [HIDEC:0x5000] Field Name Bits Default Description VENDOR_ID 15:0 0x1002 This field identifies the manufacturer of the device. Vendor ID register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-60 Proprietary...
  • Page 67 This bit is set when a device completes a Request using Completer Abort Completion Status. RECEIVED_TARGET_ABORT 0=Inactive 1=Active RECEIVED_MASTER_ABORT 0=Inactive 1=Active SIGNALED_SYSTEM_ERROR This bit must be set whenever the device asserts SERR#. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-61...
  • Page 68 LATENCY - R - 8 bits - [CFGF0_DEC:0xD] [HIDEC:0x500D] Field Name Bits Default Description LATENCY_TIMER Primary/Master latency timer does not apply to PCI Express. Regis- ter is hardwired to 0. Latency Timer register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-62 Proprietary...
  • Page 69 PFTCH_REG_EN (R) 0=Not prefetchable REG_BASE_LO 31:16 Use only lower 32-bit register base address Base address low register for registers in 64-bit address mode or base address in 32bit mode © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-63...
  • Page 70 CAPABILITIES_PTR - R - 32 bits - [CFGF0_DEC:0x34] [HIDEC:0x5034] Field Name Bits Default Description CAP_PTR 0x50 50=Point to PMI Capability Capabilities Pointer. INTERRUPT_LINE - RW - 8 bits - [CFGF0_DEC:0x3C] [HIDEC:0x503C] Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-64 Proprietary...
  • Page 71 PMI_PMC_REG - R - 16 bits - [CFGF0_DEC:0x52] [HIDEC:0x5052] Field Name Bits Default Description PMI_VERSION 2=Compliant with PMI Specification version 1.1 PMI_PME_CLOCK Does not apply to PCI Express. Hardwired to 0. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-65...
  • Page 72 Interrupt Message Number. The PCI Express Capabilities register identifies PCI Express device type and associated capabilities. DEVICE_CAP - R - 32 bits - [CFGF0_DEC:0x5C] [HIDEC:0x505C] Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-66 Proprietary...
  • Page 73 Description CORR_ERR This bit indicates status of correctable errors detected. NON_FATAL_ERR This bit indicates status of Nonfatal errors detected. FATAL_ERR This bit indicates status of Fatal errors detected. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-67...
  • Page 74 This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: 000001b X1 000010b X2 000100b X4 001000b X8 001100b X12 010000b X16 100000b X32 All other encodings are reserved. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-68 Proprietary...
  • Page 75 MSI_MSG_ADDR_LO - RW - 32 bits - [CFGF0_DEC:0x84] [HIDEC:0x5084] Field Name Bits Default Description MSI_MSG_ADDR_LO 31:2 System-specified message lower address. MSI Message Lower Address. MSI is assumed to be in 64 bit mode all the time. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-69...
  • Page 76 The Uncorrectable Error Status register reports error status of individual error sources on a PCI Express device. PCIE_UNCORR_ERR_MASK - RW - 32 bits - [CFGF0_DEC:0x108] [HIDEC:0x5108] Field Name Bits Default Description TRN_ERR_MASK Training Error Mask M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-70 Proprietary...
  • Page 77 Replay Timer Timeout Mask The Correctable Error Mask register controls reporting of individual correctable errors by device to the PCI Express Root Complex via a PCI Express error Message. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-71...
  • Page 78 F1_DEVICE_ID - R - 16 bits - [CFGF1_DEC:0x2] [HIDEC:0x5402] Field Name Bits Default Description F1_DEVICE_ID 15:0 This field identifies the particular device. This identifier is allocated by the vendor. Device ID register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-72 Proprietary...
  • Page 79 Description F1_SUB_CLASS_INF The Sub Class Code register is read-only and is used to identify a more specific function of the device. 0=VGA device 1=Extended graphics Sub Class Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-73...
  • Page 80 F1_REG_BASE_LO - RW - 32 bits - [CFGF1_DEC:0x10] [HIDEC:0x5414] Field Name Bits Default Description F1_BLOCK_REG_BIT (R) 0=Memory space base address F1_BLOCK_REG_TYPE (R) 2=Locate anywhere in 64-bit address space M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-74 Proprietary...
  • Page 81 F1_MIN_GRANT - R - 8 bits - [CFGF1_DEC:0x3E] [HIDEC:0x543E] Field Name Bits Default Description F1_MIN_GNT Registers do not apply to PCI Express. Hardwired to 0. MIN_GNT register. F1_MAX_LATENCY - R - 8 bits - [CFGF1_DEC:0x3F] [HIDEC:0x543F] © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-75...
  • Page 82 F1_PMI_D2_SUPPORT 1=Support D2 Power Management State. F1_PMI_PME_SUPPORT 15:11 For a device, this indicates the power states in which the device may generate a PME. Power Management Capabilities Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-76 Proprietary...
  • Page 83 11:9 This field indicates the acceptable latency that an Endpoint can with- stand due to the transition from L1 state to the L0 state. F1_ATTN_BUTTON_PRESENT 0=Attention Button Present © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-77...
  • Page 84 Non-Posted Requests on its own behalf (using the Port's own Requester ID) which have not been completed. The Device Status register provides information about PCI Express device specific parameters. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-78...
  • Page 85 The Link Status register provides information about PCI Express Link specific parameters. PCIE_RESERVED - R - 32 bits - PCIEIND:0x0 Field Name Bits Default Description PCIE_RESERVED 31:0 0xffffffff Reserved for future use PCIE Reserved Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-79...
  • Page 86 TLP transmission made since FC initialization, modulo 256 TX_CREDITS_CONSUMED_CPLH 23:16 For completion TLP header, total number of FC units consumed by TLP transmission made since FC initialization, modulo 256 TX Header Credits Consumed Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-80 Proprietary...
  • Page 87 FC initialization, modulo 4096 TX_CREDITS_LIMIT_NPD 23:12 For non-posed TLP data, total number of FC units advertised by the receiver since FC initialization, modulo 4096 TX Data Credits Limit Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-81...
  • Page 88 NOTE: Bits 0:11 of this field are hardwired to ZERO. PCIE_TX_GART_DISCARD_RD_ADDR_HI - RW - 32 bits - PCIEIND:0x12 Field Name Bits Default Description GART_DISCARD_RD_ADDR_HI Upper address where GART should send reads that are suppose to be discarded M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-82 Proprietary...
  • Page 89 1=A request was attempted with the address out of the GART range GART_INVALID_READ Indicates an invalid read was attempted 0=No errors 1=A read was attempted with the W bit not set in the gart entry © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-83...
  • Page 90 GART_TLB2_DATA 25:0 Data for TLB GART_TLB2_VALID Valid bit for TLB GART debug registers - Data and valid bit on TLB2 PCIE_TX_GART_TLB3_DATA - R - 32 bits - PCIEIND:0x26 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-84 Proprietary...
  • Page 91 PCIE_TX_GART_TLB9_DATA - R - 32 bits - PCIEIND:0x2C Field Name Bits Default Description GART_TLB9_DATA 25:0 Data for TLB GART_TLB9_VALID Valid bit for TLB GART debug registers - Data and valid bit on TLB9 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-85...
  • Page 92 PCIE_TX_GART_TLB16_DATA - R - 32 bits - PCIEIND:0x33 Field Name Bits Default Description GART_TLB16_DATA 25:0 Data for TLB GART_TLB16_VALID Valid bit for TLB GART debug registers - Data and valid bit on TLB16 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-86 Proprietary...
  • Page 93 PCIE_TX_GART_TLB21_DATA - R - 32 bits - PCIEIND:0x38 Field Name Bits Default Description GART_TLB21_DATA 25:0 Data for TLB GART_TLB21_VALID Valid bit for TLB GART debug registers - Data and valid bit on TLB21 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-87...
  • Page 94 PCIE_TX_GART_TLB27_DATA - R - 32 bits - PCIEIND:0x3E Field Name Bits Default Description GART_TLB27_DATA 25:0 Data for TLB GART_TLB27_VALID Valid bit for TLB GART debug registers - Data and valid bit on TLB27 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-88 Proprietary...
  • Page 95 0=30 credits 1=64 credits 2=16 credits 3=8 credits FC_NP_CREDITS 0=2 credits 1=4 credits 2=1 credit 3=reserved FC_CPL_CREDITS 0=128 credits 1=64 credits 2=32 credits 3=16 credits Flow Control Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-89...
  • Page 96 RX_GENONENAK Gen one Nak only until the next ACK RX_UNLOCK_ON (R) Unlock msg received RX Control Register PCIE_RX_NUM_NACK - R - 32 bits - PCIEIND:0x71 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-90 Proprietary...
  • Page 97 RX TLP Header Register PCIE_RX_TLP_HDR3 - R - 32 bits - PCIEIND:0x78 Field Name Bits Default Description RX_TLP_HDR3 31:0 Contents of the last received TLP Header (bits 127:96) © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-91...
  • Page 98 PCIE_RX_CREDITS_ALLOCATED_D - R - 32 bits - PCIEIND:0x7F Field Name Bits Default Description RX_CREDITS_ALLOCATED_PD 11:0 For posted TLP data, the number of FC units granted to transmitter since initialization, modulo 4096 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-92 Proprietary...
  • Page 99 PCIE_RX_MAL_TLP_COUNT - R - 32 bits - PCIEIND:0x84 Field Name Bits Default Description RX_MAL_TLP_COUNT 11:0 Record the number of malfunction TLPs received PCIE_RX_ERR_LOG - RW - 32 bits - PCIEIND:0x85 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-93...
  • Page 100 CI_HANG_TIMER[0] 1 to enable the Hang timer When non-zero => when RBBM or HDP is stalled for amount of clks request is dropped, and dummy data is taken for readback M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-94...
  • Page 101 Default Description LC_CURRENT_STATE Current LC State LC_PREV_STATE1 13:8 1st Previous LC State LC_PREV_STATE2 21:16 2nd Previous LC State LC_PREV_STATE3 29:24 3rd Previous LC State Link Control State Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-95...
  • Page 102 Description LC_PREV_STATE20 20th Previous LC State LC_PREV_STATE21 13:8 21st Previous LC State LC_PREV_STATE22 21:16 22nd Previous LC State LC_PREV_STATE23 29:24 23rd Previous LC State Link Control State Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-96 Proprietary...
  • Page 103 1=Aggressive TXCLK clock gating. All TXCLK going to bif_core is OFF during L1 & L2/L3 P_PLL_BUF_PDNB 0=Turn off 10X CLKBUF inside PHY during L1 & L2/L3 1=Keep 10X CLKBUF running inside PHY © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-97...
  • Page 104 P_DESKEW_BUF_OVERFLOW_11 Symbol skew buffer over/underflow: lane 11 P_DESKEW_BUF_OVERFLOW_12 Symbol skew buffer over/underflow: lane 12 P_DESKEW_BUF_OVERFLOW_13 Symbol skew buffer over/underflow: lane 13 P_DESKEW_BUF_OVERFLOW_14 Symbol skew buffer over/underflow: lane 14 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-98 Proprietary...
  • Page 105 => Lane 15 (0 = OK, 1 = error), etc P_DISPARITY_ERR_2 Indicates which lane has the link error: bit15 => Lane 15 (0 = OK, 1 = error), etc © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-99...
  • Page 106 1=Inserting error on Transmitting Lane2 by replacing one symbol with an invalid symbol P_INSERT_ERROR_3 0=Normal Operation 1=Inserting error on Transmitting Lane3 by replacing one symbol with an invalid symbol M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-100 Proprietary...
  • Page 107 PHY IMPEDANCE CONTROL STRENGTH REGISTER PCIE_P_IMP_CNTL_UPDATE - RW - 32 bits - PCIEIND:0xC1 Field Name Bits Default Description P_IMP_PAD_UPDATE_RATE PAD's update interval P_IMP_PAD_SAMPLE_DELAY 12:8 Sampling window P_IMP_PAD_INC_THRESHOLD 20:16 0x18 Incremental resolution © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-101...
  • Page 108 N parameter of Bad symbols (can be 1 or more) P_SYMSYNC_PAD_MODE 19:18 Mode select of Good known symbols for replacement of the Bad symbols Reserved SYMSYNC Control Registers M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-102 Proprietary...
  • Page 109 PCIE_P_DECODE_ERR_CNT_5 - R - 32 bits - PCIEIND:0xF5 Field Name Bits Default Description CODE_ERR_CNT_5 15:0 Decoder Error Counter DISPARITY_ERR_CNT_5 31:16 Disparity Error Counter Receiver Decoder Error Counter for Lane 5 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-103...
  • Page 110 Disparity Error Counter Receiver Decoder Error Counter for Lane 11 PCIE_P_DECODE_ERR_CNT_12 - R - 32 bits - PCIEIND:0xFC Field Name Bits Default Description CODE_ERR_CNT_12 15:0 Decoder Error Counter M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-104 Proprietary...
  • Page 111 DO NOT Force Phy reset (PL) when hot reset is active PR_DLY_SEL 15:14 Select the delay between link-down or hot-reset to the phy reset assertion 0=0 msec 1=4 msec 2=8 msec 3=16 msec © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-105...
  • Page 112 PCIE Indirect Register Aperture Index Register PCIE_DATA - RW - 32 bits - HIDEC:0x38 Field Name Bits Default Description PCIE_DATA 31:0 Indirect aperture data PCIE Indirect Register Aperture Data Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-106 Proprietary...

  • Page 113: Pcie Registers

    PCIE_PRBS23_BITCNT2 - RW - 32 bits - PCIEIND:0x404 Field Name Bits Default Description PRBS23_BITCNT 31:0 A 32-bit counter to enable BER measurement by freezing error counter for Lane2 PRBS23 registers for testing the PHY © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-107...
  • Page 114 PCIE_PRBS23_BITCNT9 - RW - 32 bits - PCIEIND:0x40B Field Name Bits Default Description PRBS23_BITCNT 31:0 A 32-bit counter to enable BER measurement by freezing error counter for Lane9 PRBS23 registers for testing the PHY M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-108 Proprietary...
  • Page 115 PCIE_PRBS23_BITCNT15 - RW - 32 bits - PCIEIND:0x411 Field Name Bits Default Description PRBS23_BITCNT 31:0 A 32-bit counter to enable BER measurement by freezing error counter for Lane15 PRBS23 registers for testing the PHY © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-109...
  • Page 116 PRBS23 registers for testing the PHY PCIE_PRBS23_ERRCNT6 - RW - 32 bits - PCIEIND:0x418 Field Name Bits Default Description PRBS23_ERRCNT (R) 31:0 Error counter for Lane6 PRBS23 registers for testing the PHY M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-110 Proprietary...
  • Page 117 PRBS23 registers for testing the PHY PCIE_PRBS23_ERRCNT13 - RW - 32 bits - PCIEIND:0x41F Field Name Bits Default Description PRBS23_ERRCNT (R) 31:0 Error counter for Lane13 PRBS23 registers for testing the PHY © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-111...
  • Page 118 Clear PRBS23 checker error registers for Lane 13 PRBS23_CLR14 Clear PRBS23 checker error registers for Lane 14 PRBS23_CLR15 Clear PRBS23 checker error registers for Lane 15 PRBS23 registers for testing the PHY M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-112 Proprietary...
  • Page 119 0=VGA controller capacity enabled 1=the device will not be recognized as the system's VGA controller Reserved SLV_ADR64_EN (R) Slave DAC Decode. Decode dual address slave cycle and using 64-bit bar © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-113...
  • Page 120 Field Name Bits Default Description PCIE_INDEX 10:0 Indirect aperture index PCIE Indirect Register Aperture Index Register PCIE_DATA - RW - 32 bits - HIDEC:0x38 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-114 Proprietary...
  • Page 121 PCIE Registers PCIE_DATA 31:0 Indirect aperture data PCIE Indirect Register Aperture Data Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-115...

  • Page 122: Vip/I2C Registers

    VIP host port channel 3 DMA interrupt. 0=No event 1=Event has occurred, interrupting if enabled DMA_VIPH3_INT_AK (W) VIP host port channel 3 DMA interrupt acknowledge/reset. 0=No effect 1=Clear status M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-116 Proprietary...
  • Page 123 Write this bit initiate I2C operation. Read this bit indicate the I2C operation is finished or not. I2C_PRESCALE 31:16 I2C clock divider to generate I2C SCL output. It also indirectly control the sampling rate. I2C control registers © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-117...
  • Page 124 I2C data interface. Programmers use this 8bits interface to write and read I2C bus data. I2C data registers. Programmers use this 8bits interface to write and read I2C bus data. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-118...

  • Page 125: Video Interface Port Host Port Registers

    VIP host port channel 3 DMA interrupt. 0=No event 1=Event has occurred, interrupting if enabled DMA_VIPH3_INT_AK (W) VIP host port channel 3 DMA interrupt acknowledge/reset. 0=No effect 1=Clear status © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-119...
  • Page 126 Description VIPH_CH0_AD Bit(3:0): FIFO address Bit(4): 0= register access, 1 = FIFO access. Bit(5): 0= register write, 1= register read. Bits(7:6): Slave device ID. VIPH0 command + address. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-120 Proprietary...
  • Page 127 Write non-zero byte count will trigger DMA. Maximum 2 jobs can be loaded into the queue any one time. Byte count of transfer requested. VIPH_CH3_SBCNT - RW - 32 bits - VIPDEC:0xC2C © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-121...
  • Page 128 Number of VIP phases before issuing time out. Set to zero means no time out VIPH_DMA_MODE 0= No DMA. 1= DMA VIPH_EN VIP Host port Enable VIPH_DV0_WID VIPH0 bus width 0=2-bit vipbus 1=4-bit vipbus M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-122 Proprietary...
  • Page 129 VIPH_CH1_ABORT Abort DMA operation through port 1 VIPH_CH2_ABORT Abort DMA operation through port 2 VIPH_CH3_ABORT Abort DMA operation through port 3 DMA transfer chunk size and abort control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-123...
  • Page 130 VIPH_REGR_DIS '0'= any host read from VIPH_REG_DATA will trigger VIP register cycle. 1= Read from VIPH_REG_DATA will not trigger VIP register cycle. VIP Host Port Time Out Status M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-124 Proprietary...
  • Page 131 VIPH_REG_DT_R (R) 31:0 Read from VIP Host Port register data port VIPH_REG_DT_W (W) 31:0 Write to VIP Host Port register data port VIP Host Port register data port © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-125...

  • Page 132: Capture Registers

    1=Event has occurred, interrupting if enabled General Interrupt Status register. These fields can be polled and acknowledged even if interrupts are disabled, or the respective fields are masked in the GEN_INT_CNTL register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-126...
  • Page 133 CAP0_BUF_PITCH - RW - 32 bits - VIPDEC:0x930 Field Name Bits Default Description CAP_BUF_PITCH 11:0 Capture 0 buffer's pitch. NOTE: Bits 0:1 of this field are hardwired to ZERO. Capture 0 buffer's pitch. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-127...
  • Page 134 Capture 0 VBI's Horizontal Width. NOTE: Bits 0:1 of this field are hardwired to ZERO. Capture 0 VBI's horizontal window CAP0_PORT_MODE_CNTL - RW - 32 bits - VIPDEC:0x94C M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-128 Proprietary...
  • Page 135 Read only. Current starting buffer. 0=Buffer 0 1=Buffer 1 CAP_START_BUF_W (W) Write only. Control starting buffer. 0=Buffer 0 1=Buffer 1 CAP_BUF_TYPE Buffer type. 0=Field 1=Alternating 2=Frame CAP_ONESHOT_MODE ONESHOT mode. 0=FIELD 1=FRAME © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-129...
  • Page 136 CAP_IMAGE_FLIP_EN 0=Normal 1=Flip CAP_ONESHOT_IMAGE_FLIP_EN 0=Normal 1=Flip CAP_VIDEO_IN_FORMAT Input format. 0=YVYU422 1=VYUY422 VBI_HORZ_DOWN 31:30 0=Normal 1=x2 2=x4 Capture 0 configuration register. CAP0_ANC0_OFFSET - RW - 32 bits - VIPDEC:0x95C M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-130 Proprietary...
  • Page 137 Default Description CAP_PRE_VID_BUF (R) Read only. Previous capture buffer. CAP_CUR_VID_BUF (R) Read only. Current Capture buffer. CAP_PRE_FIELD (R) Read only. Previous field. CAP_CUR_FIELD (R) Read only. Current field. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-131...
  • Page 138 CAP0_ANC3_OFFSET - RW - 32 bits - VIPDEC:0x98C Field Name Bits Default Description CAP_ANC3_OFFSET 31:0 Starting address NOTE: Bits 0:1 of this field are hardwired to ZERO. Capture 0 ANC 3 starting address. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-132 Proprietary...
  • Page 139 Capture 0 VBI Buffer 3 Interrupt enable. 0=Disable 1=Enable CAP0_ANC2_INT_EN Capture 0 ANC Buffer 2 Interrupt enable. 0=Disable 1=Enable CAP0_ANC3_INT_EN Capture 0 ANC Buffer 3 Interrupt enable. 0=Disable 1=Enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-133...
  • Page 140 CAP0_ANC1_INT_AK (W) ANC buffer 1 interrupt acknowledgment. 0=No effect 1=Clear status CAP0_VBI2_INT (R) Read only. VBI buffer 2 interrupt status. 0=No event 1=Event has occurred, interrupting if enabled M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-134 Proprietary...
  • Page 141 Read only. ANC buffer 3 interrupt status. 0=No event 1=Event has occurred, interrupting if enabled CAP0_ANC3_INT_AK (W) ANC buffer 3 interrupt acknowledgment. 0=No effect 1=Clear status Capture port interrupt control. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-135...

  • Page 142: Vip Host Port Dma Registers

    VIP host port channel 3 DMA interrupt. 0=No event 1=Event has occurred, interrupting if enabled DMA_VIPH3_INT_AK (W) VIP host port channel 3 DMA interrupt acknowledge/reset. 0=No effect 1=Clear status M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-136 Proprietary...
  • Page 143 2=[7:0] =[31:24], [15:8] = [23:16], [23:16] = [15:8], [31:24] = [7:0] 3=Undefined TRANSFER_SOURCE Address space of source data. 0=Transfer from memory 1=Transfer from VIPH TRANSFER_DEST Address space of destination data. 0=Transfer to memory 1=Transfer to VIPH © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-137...
  • Page 144 2=[7:0] =[31:24], [15:8] = [23:16], [23:16] = [15:8], [31:24] = [7:0] 3=Undefined TRANSFER_SOURCE Address space of source data. 0=Transfer from memory 1=Transfer from VIPH TRANSFER_DEST Address space of destination data. 0=Transfer to memory 1=Transfer to VIPH M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-138 Proprietary...
  • Page 145 VIPH DMA Channel 2 Endian swap control. 0=No swap 1=8bit swap 2=16bit swap 3=reserved DMA_VIPH1_TABLE_SWAP VIPH DMA Channel 1 Endian swap control. 0=No swap 1=8bit swap 2=16bit swap 3=reserved © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-139...
  • Page 146 DMA_VIP2_TABLE_ADDR - W - 32 bits - VIPDEC:0xA40 Field Name Bits Default Description DMA_VIPH_TABLE_ADDR 31:0 This points to first entry in the DMA table. VIP Port 2 DMA table starting address M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-140 Proprietary...
  • Page 147 DMA_VIPH3_ACTIVE - R - 32 bits - VIPDEC:0xA54 Field Name Bits Default Description DMA_VIPH_TABLE_ADDR_ACT 31:0 This points to the current active entry in the DMA table. VIP Port 3 DMA Current table address © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-141...
  • Page 148 Soft reset. Reset the DMA and job queue. DMA_VIPH2_RESET Soft reset. Reset the DMA and job queue. DMA_VIPH3_RESET Soft reset. Reset the DMA and job queue. VIP Host Port DMA abort control registers M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-142 Proprietary...

  • Page 149: Gpio Registers

    VIP host port channel 3 DMA interrupt. 0=No event 1=Event has occurred, interrupting if enabled DMA_VIPH3_INT_AK (W) VIP host port channel 3 DMA interrupt acknowledge/reset. 0=No effect 1=Clear status © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-143...
  • Page 150 VIP_DEVICE (R) Indicates if any slave VIP host devices drove this pin low during reset. 0=No slave VIP host port devices present 1=Slave VIP host port devices present Reserved M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-144 Proprietary...
  • Page 151 1=If VIP host port interrupt using input instead of polling, then ZV_LCDCNTL(2) pin used as interrupt input. Reserved Reserved ROM_CLK_DIVIDE 20:16 ROM clock divider STR_ROMCLK Extend ROM cycle VIP_INTERNAL_DEBUG_SEL 24:22 Legacy. Not used. GPIO pin mux control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-145...
  • Page 152 28:24 When the SECTOR_ERASE bit is set to 1, this field specifies which sector to erase. ROM_SCLK_SRC_SEL 30:29 0=SCLK/3 1=SCLK/2 2=SCLK/1 3=SCLK/1 Second SPI Serial ROM Control register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-146 Proprietary...

  • Page 153: Vip Miscellaneous Registers

    GPIO pads output enable register GPIOPAD_Y - RW - 32 bits - VIPDEC:0x1A4 Field Name Bits Default Description GPIO_Y (R) 17:0 GPIO pads input. GPIO pad input read back. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-147...
  • Page 154 VIP_HW_DEBUG - RW - 32 bits - VIPDEC:0x1CC Field Name Bits Default Description VIP_HW_0_DEBUG Not used. VIP_HW_1_DEBUG Not used. VIP_HW_2_DEBUG Not used. VIP_HW_3_DEBUG Not used. VIP_HW_4_DEBUG Not used. VIP_HW_5_DEBUG Not used. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-148 Proprietary...
  • Page 155 DMA_VIPH_MISC_CNTL - RW - 32 bits - VIPDEC:0xA14 Field Name Bits Default Description DMA_VIPH_READ_TIMER VIPH DMA read timer. DMA_VIPH_READ_TIMEOUT_TO_PIORITY_EN 0=Disable 1=Enable DMA_VIPH_READ_TIMEOUT_STATUS (R) 0=Normal 1=Timeout VIPH DMA misc control register. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-149...
  • Page 156 Output for GPIO[26]. 0=GPIO output is low for this pin, if mask and output are enabled. 1=GPIO output is high for this pin, if mask and output are enabled. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-150...
  • Page 157 1=This pin was high at time of read. VIPPAD_Y_VID 15:8 Input readback of GPIO[34:27]. 0=This pin was low at time of read. 1=This pin was high at time of read. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-151...
  • Page 158 Bits Default Description PWM_INC PWM increment PWM_CLK_DIV 11:8 PWM clock divider PWM_OUT_EN 0=PWM output disabled. 1=PWM output enabled. PSYNC pin becomes output enabled and drives out PWM signal. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-152 Proprietary...
  • Page 159 1=Event has occurred, interrupting if enabled DMA_VIPH3_INT_AK (W) VIP host port channel 3 DMA interrupt acknowledge/reset. 0=No effect 1=Clear status I2C_INT (R) I2C interrupt. 0=No event 1=Event has occurred, interrupting if enabled © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-153...
  • Page 160 1=Event has occurred, interrupting if enabled General Interrupt Status register. These fields can be polled and acknowledged even if interrupts are disabled, or the respective fields are masked in the GEN_INT_CNTL register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-154...

  • Page 161: Clock Generator Registers

    1=For debug purpose: when SW_DIR_CONTROL is set, this value replicates the value of the CTLREQ once the command has been received and it is safe to send another request SPLL control register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-155...
  • Page 162 1=For debug purpose: when SW_DIR_CONTROL is set, this value replicates the value of the CTLREQ once the command has been received and it is safe to send another request M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-156...
  • Page 163 1=SCLK power management off SCLK_TURNOFF 1=Turn off SCLK, SW direct control, override HW pwrmgt control SPLL_TURNOFF 1=Power down SPLL, SW direct control, override HW pwrmgt con- trol SPARE Reserved © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-157...
  • Page 164 PROG_SHUTOFF is set DYN_STOP_LAT 14:11 delay between idle state get detected till sclk get turned off ACTIVE_ENABLE_LAT 19:15 delay between clock_enable changes to cg_rbbm_active changes M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-158 Proprietary...
  • Page 165 (in sclk cycle) between voltage goes to normal till sclk speed goes back to normal Static screen mode voltage control VIP_DYN_CNTL - RW - 32 bits - CLKIND:0x14 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-159...
  • Page 166 0=MC_HOST branch is off 1=MC_HOST branch is on MC_HOST_PROG_SHUTOFF 1=MC_HOST branch shutoff with PROG_DELAY_VALUE delay MC_HOST_PROG_DELAY_VALUE 11:4 Delay MC_HOST clock on/off by number of cycles MC_HOST dynamic clock gating control M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-160 Proprietary...
  • Page 167 MRDCKB0_SOUTSEL 0=DLL output clock 1=QS pin 2=QS delayed 2 elements 3=QS delayed 4 elements MRDCKB1_SOUTSEL 0=DLL output clock 1=QS pin 2=QS delayed 2 elements 3=QS delayed 4 elements © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-161...
  • Page 168 0x2000 number of PCIE refclk cycles need to wait before PLL get locked SPLL_RESET_TIME 31:16 0x1f4 PLL reset pulse width (in PCIE refclk cycles SPLL related timing counter M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-162 Proprietary...
  • Page 169 0=High Gain 1=Low Gain CG_CLK_TO_OUTPIN 0=Disabled 1=Send out selected clock for jitter test OSC_USE_CORE 0=Pad routing OSC 1=Core routing OSC VOL_DROP_CNT - RW - 32 bits - CLKIND:0x36 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-163...
  • Page 170 1=All 8 JTAG cycles have been completed since the last write to CG_TC_JTAG_0 TDO readback and status bits for the CG JTAG interface described in more detail in the CG_TC_JTAG_0 register description. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-164...

  • Page 171: Vga Registers

    1 = HSYNC pulse active low The convention of VGA is to use active low VSYNC for 400 (and 200) and 480 line modes. Active high is normally used for 350 line modes. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-165...
  • Page 172 DAC comparator read back. Used for monitor detection. Mirror of DAC_CMP_OUTPUT@DAC_CNTL. See description there. CRT_INTR CRT Interrupt: 0=Vertical retrace interrupt is cleared 1=Vertical retrace interrupt is pending Input Status 0 Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-166 Proprietary...
  • Page 173 These two bits are connected to two of the eight colour outputs (P7:P0) of the attribute controller. Connections are controlled by ATTR12(5,4) as follows: 0=P2,P0 1=P5,P4 2=P3,P1 3=P7,P6 Input Status 1 Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-167...

  • Page 174: Vga Dac Control Registers

    Default Description DAC_W_INDEX Sets the index for a palette (DAC) write operation. Index auto-incre- ments after every third write of DAC_DATA. Also see DAC_R_INDEX. Palette (DAC) Write Index M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-168 Proprietary...

  • Page 175: Vga Sequencer Registers

    0=Disable write to memory map 2 1=Enable write to memory map 2 SEQ_MAP3_EN Enable map 3 0=Disable write to memory map 3 1=Enable write to memory map 3 Map Mask Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-169...
  • Page 176 0x3C5, for the next SEQ read/write operation. SEQ Index Register SEQ8_DATA - RW - 8 bits - DISPDEC:0x3C5 Field Name Bits Default Description SEQ_DATA SEQ data indirect access SEQ Data Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-170 Proprietary...

  • Page 177: Vga Crt Registers

    H blanking bits 4-0 respectively. These are the five low-order bits (of six bits in total) of horizontal character count for triggering the end of the horizontal blanking pulse. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-171...
  • Page 178 CRT06 register. V_DISP_END_B9 End V Display Bit 9 (CRT12). Bit 9 of 10-bit vertical count for V Dis- play enable end (for functional description see CRT12 register). M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-172 Proprietary...
  • Page 179 'start' value. In EGA when the 'end' value is less, the cursor is a full block cursor the same height as the character cell. CURSOR_DISABLE Cursor on/off. 0=on 1=off Cursor Start Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-173...
  • Page 180 CRT0C + CRT0D. In other words, if CRT0C + CRT0D is changed, the cursor still pints to the same character as before. Cursor Location (High Byte) Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-174...
  • Page 181 The high-order bits are CRT07 [1:6] in the CRT overflow register. Vertical Display Enable End Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-175...
  • Page 182 Blanking register (CRT15) minus one. End Vertical Blanking Register CRT17 - RW - 8 bits - VGACRTIND:0x17 Field Name Bits Default Description RA0_AS_A13B Compatibility Mode: RA1_AS_A14B Select Row Scan Counter: M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-176 Proprietary...
  • Page 183 This register is used to read the data in the Graphics Controller CPU data latches. The Graphics Controller Read Map Select register bits 0 and 1 determines which byte is read back. RAM Data Latch Readback Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-177...

  • Page 184: Vga Graphics Registers

    If Colour Don't Care bit for one map is a logical zero, the latched data from the map is excluded from the compare, and only the remaining three bits are compared to generate bus data. Colour Compare Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-178 Proprietary...
  • Page 185 256 Colour Mode. This bit also controls how data from memory is loaded into the shift registers. 0=Use shift register mode as per GRPH_OES 1=256 color mode, read as packed pixels, ignore GRPH_OES Graphics Mode Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-179...
  • Page 186 1=Use map 3 for read mode 1 Colour Don't Care Register GRA08 - RW - 8 bits - VGAGRPHIND:0x8 Field Name Bits Default Description GRPH_BMSK Bit Mask Bit Mask Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-180 Proprietary...

  • Page 187: Vga Attribute Registers

    Colour is disabled for those bits that are set to logical 0; enabled for those bits set to logical 1. Palette Register 1 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-181...
  • Page 188 Colour is disabled for those bits that are set to logical 0; enabled for those bits set to logical 1. Palette Register 7 ATTR08 - RW - 8 bits - VGAATTRIND:0x8 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-182 Proprietary...
  • Page 189 0; enabled for those bits set to logical 1. Palette Register Dh (13) ATTR0E - RW - 8 bits - VGAATTRIND:0xE Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-183...
  • Page 190 ATTR11 - RW - 8 bits - VGAATTRIND:0x11 Field Name Bits Default Description ATTR_OVSC Overscan Colour Overscan Colour Register ATTR12 - RW - 8 bits - VGAATTRIND:0x12 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-184 Proprietary...
  • Page 191 8-bit colour, used for rapid colour set switching (addressing different parts of the DAC colour lookup table). The lower order bits are in registers ATTR00-0F. Colour Select Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-185...

  • Page 192: Vga Miscellaneous Registers

    1=Force SEQ_DOT8 =1, VGA_CKSEL = 0 for functionality VGAREG_LINECMP_COMPATIBILITY_SEL Selects point at which line compare is activated 0=line==line_cmp(default). As per VGA specification 1=line>line_cmp. As per legacy ATI VGA controllers VGA Render control Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-186 Proprietary...
  • Page 193 VGA_SURFACE_PITCH_SELECT - RW - 32 bits - DISPDEC:0x30C Field Name Bits Default Description VGA_SURFACE_PITCH_SELECT Selects the pitch of the display buffer 0=768 pixels 1=1024 pixels 2=1280 pixels 3=1408 pixels © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-187...
  • Page 194 Does soft reset for VGA, does not reset the registers 0=VGA running in normal operating mode 1=Soft Reset to VGA VGA_TEST_RESET_CONTROL Not used VGAHDP control register VGA_CACHE_CONTROL - RW - 32 bits - DISPDEC:0x32C M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-188 Proprietary...
  • Page 195 2=rotation 180 degrees, displays do not interchange VGA_DISP_h_disp_width and VGA_DISP_v_disp_height parame- ters 3=rotation 270 degrees, displays do interchange VGA_DISP_h_disp_width and VGA_DISP_v_disp_height parame- ters VGA-Display1 interface control register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-189...
  • Page 196 Display switch status 0=No event 1=Event has occurred, interrupting if enabled VGA_MODE_AUTO_TRIGGER_STATUS (R) VGA mode auto trigger status 0=No event 1=Event has occurred, interrupting if enabled VGA status register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-190 Proprietary...
  • Page 197 1=Event has occurred VGA_DISPLAY_SWITCH_INT_STATUS (R) Display switch interrupt status 0=No event 1=Event has occurred VGA_MODE_AUTO_TRIGGER_INT_STATUS VGA mode auto trigger interrupt status 0=No event 1=Event has occurred VGA Interrupt status register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-191...
  • Page 198 0=Uses vga main render state machine virtual vertical retrace 1=reserved 2=Uses CRTC1 vblank signal 3=Uses CRTC2 vblank signal VGA_READBACK_SENSE_SWITCH_SELECT selects the source for the SENSE_SWITCH readback register bit 0=Uses CRTC1 sense_switch signal 1=Uses CRTC2 sense_switch signal M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-192 Proprietary...
  • Page 199 VGA test control register VGA_DEBUG_READBACK_INDEX - RW - 32 bits - DISPDEC:0x358 Field Name Bits Default Description VGA_DEBUG_READBACK_INDEX Index for the VGA debug readback VGA debug readback index register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-193...
  • Page 200 The convention of VGA is to use active high VSYNC for 400 (and 200) line modes. Active low is normally used for 350 and 480 line modes. Miscellaneous Output Register (Write) M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-194 Proprietary...
  • Page 201 0x3C5, for the next SEQ read/write operation. SEQ Index Register SEQ8_DATA - RW - 8 bits - DISPDEC:0x3C5 Field Name Bits Default Description SEQ_DATA SEQ data indirect access SEQ Data Register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-195...
  • Page 202 VGA graphics index as per VGA specified by IBM GRPH Index Register GRPH8_DATA - RW - 8 bits - DISPDEC:0x3CF Field Name Bits Default Description GRPH_DATA GRPH data indirect access GRPH Data Register M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-196 Proprietary...
  • Page 203 VGA_MEM_READ_PAGE_ADDR - RW - 32 bits - DISPDEC:0x3C Field Name Bits Default Description VGA_MEM_READ_PAGE0_ADDR Read page 0 address VGA_MEM_READ_PAGE1_ADDR 25:16 Read page 1 address VGA read page register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-197...

  • Page 204: Display Controller Registers

    This field is don't care when D1GRPH_TILED = 1 (micro tiled mode). Display does not support macro-linear and micro-tiled surfaces. When D1GRPH_TILED = 1, addressing mode is macro-tiled and micro-tiled. 0=macro-linear (and micro-linear) 1=macro-tiled (and micro-linear) M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-198 Proprietary...
  • Page 205 Primary surface address for primary graphics in byte. It is 4K byte aligned. NOTE: Bits 0:10 of this field are hardwired to ZERO. Primary surface address for primary graphics in byte. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-199...
  • Page 206 Field Name Bits Default Description D1GRPH_X_START 12:0 Primary graphic X start coordinate relative to the desktop coordi- nates. Primary graphic X start coordinate relative to the desktop coordinates. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-200 Proprietary...
  • Page 207 0=No update pending 1=Update pending D1GRPH_MODE_UPDATE_TAKEN (R) Primary graphics update taken status for mode registers. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-201...
  • Page 208 DMIF and is updated on SOF or horizontal surface update. The snap- shot is triggered by writing 1 into field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC register D1CRTC_SNAPSHOT_STATUS. Snapshot of primary graphics surface address in use M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-202 Proprietary...

  • Page 209: Primary Display Video Overlay Control Registers

    Primary overlay pixel depth and format. D1OVL_CONTROL2 - RW - 32 bits - DISPDEC:0x6188 Field Name Bits Default Description D1OVL_HALF_RESOLUTION_ENABLE Primary overlay half resolution control 0=disable 1=enable Primary overlay half resolution control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-203...
  • Page 210 Primary overlay Y start coordinate relative to the desktop coordi- nates. D1OVL_X_START 28:16 Primary overlay X start coordinate relative to the desktop coordi- nates. Primary overlay X, Y start coordinate relative to the desktop coordinates. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-204 Proprietary...
  • Page 211 SOF or horizontal surface update. The snapshot is trig- gered by writing 1 into field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC register D1CRTC_SNAPSHOT_STATUS. Snapshot of primary overlay surface address in use © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-205...

  • Page 212: Primary Display Video Overlay Transform Registers

    NOTE: Bits 0:6 of this field are hardwired to ZERO. D1OVL_MATRIX_SIGN_1_4 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-206 Proprietary...
  • Page 213 NOTE: Bits 0:4 of this field are hardwired to ZERO. D1OVL_MATRIX_SIGN_3_1 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-207...
  • Page 214 NOTE: Bits 0:6 of this field are hardwired to ZERO. D1OVL_MATRIX_SIGN_3_4 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-208 Proprietary...

  • Page 215: Primary Display Video Overlay Gamma Correction Registers

    24:16 0x100 Primary overlay gamma correction non-linear slope for input 40-7F. Format fix-point 1.8 (0.00 to +1.99). Primary overlay gamma correction non-linear offset and slope for input 40-7F. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-209...
  • Page 216 Primary overlay gamma correction non-linear offset for input 1C0-1FF. Format fix-point 10.1 (0.0 to +1023.5). D1OVL_PWL_1C0TO1FF_SLOPE 24:16 0x100 Primary overlay gamma correction non-linear slope for input 1C0-1FF. Format fix-point 1.8 (0.00 to +1.99). M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-210 Proprietary...
  • Page 217 Primary overlay gamma correction non-linear slope for input 300-33F. Format fix-point 1.8 (0.00 to +1.99). Primary overlay gamma correction non-linear offset and slope for input 300-33F. D1OVL_PWL_340TO37F - RW - 32 bits - DISPDEC:0x62C0 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-211...
  • Page 218 24:16 0x100 Primary overlay gamma correction non-linear slope for input 3C0-3FF. Format fix-point 1.8 (0.00 to +1.99). Primary overlay gamma correction non-linear offset and slope for input 3C0-3FF. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-212 Proprietary...

  • Page 219: Primary Display Graphics And Overlay Blending Registers

    Global overlay alpha for use in key mode and global alpha modes. See D1OVL_ALPHA_MODE register filed for more details Global overlay alpha for use in key mode and global alpha modes. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-213...
  • Page 220 31:16 Primary graphics keyer green component upper limit. Note: If the graphic component is less than 16 bit, msbs are all zeros. Primary graphics keyer green component range M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-214 Proprietary...
  • Page 221 25:16 Primary overlay keyer green component upper limit. Note: If the overlay component is less than 16 bit, msbs are all zeros. Primary overlay keyer green component range © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-215...
  • Page 222 23:16 Primary overlay keyer alpha component upper limit. Note: If the overlay component is less than 16 bit, msbs are all zeros. Primary overlay keyer alpha component range M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-216 Proprietary...

  • Page 223: Primary Display Color Matrix Transform Registers

    NOTE: Bits 0:4 of this field are hardwired to ZERO. D1COLOR_MATRIX_SIGN_1_2 Sign bit of combined matrix constant Combined matrix constant C12 of RGB->YCbCr, contrast and brightness adjustment for primary display. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-217...
  • Page 224 NOTE: Bits 0:4 of this field are hardwired to ZERO. D1COLOR_MATRIX_SIGN_2_3 Sign bit of combined matrix constant Combined matrix constant C23 of RGB->YCbCr, contrast and brightness adjustment for primary display. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-218 Proprietary...
  • Page 225 NOTE: Bits 0:4 of this field are hardwired to ZERO. D1COLOR_MATRIX_SIGN_3_3 Sign bit of combined matrix constant Combined matrix constant C33 of RGB->YCbCr, contrast and brightness adjustment for primary display. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-219...
  • Page 226 NOTE: Bits 0:6 of this field are hardwired to ZERO. D1COLOR_MATRIX_SIGN_3_4 Sign bit of combined matrix constant Combined matrix constant C34 of RGB->YCbCr, contrast and brightness adjustment for primary display. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-220 Proprietary...

  • Page 227: Primary Display Subsampling Registers

    1=subsample CrCb (RB) by using 2 tap average method 2=subsample CrCb (RB) by using 1 tap on even pixel 3=subsample CrCb (RB) by using 1 tap on odd pixel Sub-sampling control for primary display. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-221...

  • Page 228: Primary Display Hardware Cursor Registers

    Primary display hardware cursor X coordinate at the hot spot relative to the desktop coordinates. Primary display hardware cursor position D1CUR_HOT_SPOT - RW - 32 bits - DISPDEC:0x6418 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-222 Proprietary...
  • Page 229 Primary display hardware cursor update taken status. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0 D1CURSOR_UPDATE_LOCK Primary display hardware cursor update lock control. 0=Unlocked 1=Locked © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-223...

  • Page 230: Primary Display Hardware Icon Registers

    Primary display hardware icon blue component of color 1. D1ICON_COLOR1_GREEN 15:8 Primary display hardware icon green component of color 1. D1ICON_COLOR1_RED 23:16 Primary display hardware icon red component of color 1. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-224 Proprietary...
  • Page 231 Primary display hardware icon update Taken status. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0 D1ICON_UPDATE_LOCK Primary display hardware icon update lock control. 0=Unlocked 1=Locked Primary display hardware icon update control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-225...

  • Page 232: Display Look Up Table Control Registers

    Linear interpolation of delta value for host read/write. The LUT index is increased by 1 when register DC_LUT_PWL_DATA is accessed. NOTE: Bits 0:5 of this field are hardwired to ZERO. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-226...
  • Page 233 Enable LUT autofill when 1 is written into this field 0=No effect 1=Start LUT autofill DC_LUT_AUTOFILL_DONE (R) LUT autofill is done 0=LUT autofill is not completed 1=LUT autofill is done LUT autofill control © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-227...

  • Page 234: Display Controller Look Up Table A Registers

    0=Green data is unsigned 1=Green data is signed DC_LUTA_DATA_G_FLOAT_POINT_EN Frame buffer green data float point enable for look-up table A. 0=Green data is fix point 1=Green data is float point M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-228 Proprietary...
  • Page 235 DC_LUTA_BLACK_OFFSET_RED - RW - 32 bits - DISPDEC:0x64CC Field Name Bits Default Description DC_LUTA_BLACK_OFFSET_RED 15:0 Black value offset of red component for LUTA. Black value offset of red component for LUTA. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-229...
  • Page 236 DC_LUTA_WHITE_OFFSET_RED - RW - 32 bits - DISPDEC:0x64D8 Field Name Bits Default Description DC_LUTA_WHITE_OFFSET_RED 15:0 0xffff White value offset of red component for LUTA White value offset of red component for LUTA M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-230 Proprietary...

  • Page 237: Secondary Display Graphics Control Registers

    This field is don't care when D2GRPH_TILED = 1 (micro tiled mode). Display does not support macro-linear and micro-tiled surfaces. When D2GRPH_TILED = 1, addressing mode is macro-tiled and micro-tiled. 0=macro-linear (and micro-linear) 1=macro-tiled (and micro-linear) © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-231...
  • Page 238 Secondary surface address for secondary graphics in byte. It is 4K byte aligned. NOTE: Bits 0:10 of this field are hardwired to ZERO. Secondary surface address for secondary graphics in byte. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-232 Proprietary...
  • Page 239 Field Name Bits Default Description D2GRPH_X_START 12:0 Secondary graphic X start coordinate relative to the desktop coordi- nates. Secondary graphic X start coordinate relative to the desktop coordinates. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-233...
  • Page 240 0=No update pending 1=Update pending D2GRPH_MODE_UPDATE_TAKEN (R) Secondary graphics update taken status for mode registers. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-234 Proprietary...
  • Page 241 DMIF and is updated on SOF or horizontal surface update. The snap- shot is triggered by writing 1 into field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC register D1CRTC_SNAPSHOT_STATUS. Snapshot of secondary graphics surface address in use © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-235...

  • Page 242: Secondary Display Video Overlay Control Registers

    D2OVL_CONTROL2 - RW - 32 bits - DISPDEC:0x6988 Field Name Bits Default Description D2OVL_HALF_RESOLUTION_ENABLE Secondary overlay half resolution control 0=disable 1=enable Secondary overlay half resolution control D2OVL_SURFACE_ADDRESS - RW - 32 bits - DISPDEC:0x6990 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-236 Proprietary...
  • Page 243 Secondary overlay Y start coordinate relative to the desktop coordi- nates. D2OVL_X_START 28:16 Secondary overlay X start coordinate relative to the desktop coordi- nates. Secondary overlay X, Y start coordinate relative to the desktop coordinates. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-237...
  • Page 244 DMIF and is updated on SOF or horizontal surface update. The snap- shot is triggered by writing 1 into field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC register D1CRTC_SNAPSHOT_STATUS. Snapshot of secondary overlay surface address in use M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-238 Proprietary...

  • Page 245: Secondary Display Video Overlay Transform Registers

    NOTE: Bits 0:6 of this field are hardwired to ZERO. D2OVL_MATRIX_SIGN_1_4 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-239...
  • Page 246 NOTE: Bits 0:4 of this field are hardwired to ZERO. D2OVL_MATRIX_SIGN_3_1 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay. D2OVL_MATRIX_COEF_3_2 - RW - 32 bits - DISPDEC:0x6A28 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-240 Proprietary...
  • Page 247 NOTE: Bits 0:6 of this field are hardwired to ZERO. D2OVL_MATRIX_SIGN_3_4 Sign bit of combined matrix constant Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-241...

  • Page 248: Secondary Display Video Overlay Gamma Correction Registers

    24:16 0x100 Secondary overlay gamma correction non-linear slope for input 40-7F. Format fix-point 1.8 (0.00 to +1.99). Secondary overlay gamma correction non-linear offset and slope for input 40-7F. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-242 Proprietary...
  • Page 249 D2OVL_PWL_1C0TO1FF - RW - 32 bits - DISPDEC:0x6AA8 Field Name Bits Default Description D2OVL_PWL_1C0TO1FF_OFFSET 10:0 0x380 Secondary overlay gamma correction non-linear offset for input 1C0-1FF. Format fix-point 10.1 (0.0 to +1023.5). © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-243...
  • Page 250 24:16 0x100 Secondary overlay gamma correction non-linear slope for input 300-33F. Format fix-point 1.8 (0.00 to +1.99). Secondary overlay gamma correction non-linear offset and slope for input 300-33F. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-244 Proprietary...
  • Page 251 24:16 0x100 Secondary overlay gamma correction non-linear slope for input 3C0-3FF. Format fix-point 1.8 (0.00 to +1.99). Secondary overlay gamma correction non-linear offset and slope for input 3C0-3FF. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-245...

  • Page 252: Secondary Display Graphics And Overlay Blending Registers

    Global overlay alpha for use in key mode and global alpha modes. See D2OVL_ALPHA_MODE register filed for more details Global overlay alpha for use in key mode and global alpha modes. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-246...
  • Page 253 31:16 Secondary graphics keyer green component upper limit. Note: If the graphic component is less than 16 bit, msbs are all zeros. Secondary graphics keyer green component range © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-247...
  • Page 254 25:16 Secondary overlay keyer blue component upper limit. Note: If the overlay component is less than 16 bit, msbs are all zeros. Secondary overlay keyer blue component range M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-248 Proprietary...
  • Page 255 23:16 Secondary overlay keyer alpha component upper limit. Note: If the overlay component is less than 16 bit, msbs are all zeros. Secondary overlay keyer alpha component range © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-249...

  • Page 256: Secondary Display Color Matrix Transform Registers

    NOTE: Bits 0:4 of this field are hardwired to ZERO. D2COLOR_MATRIX_SIGN_1_3 Sign bit of combined matrix constant Combined matrix constant C13 of RGB->YCbCr, contrast and brightness adjustment for secondary display. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-250 Proprietary...
  • Page 257 NOTE: Bits 0:4 of this field are hardwired to ZERO. D2COLOR_MATRIX_SIGN_2_3 Sign bit of combined matrix constant Combined matrix constant C23 of RGB->YCbCr, contrast and brightness adjustment for secondary display. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-251...
  • Page 258 NOTE: Bits 0:4 of this field are hardwired to ZERO. D2COLOR_MATRIX_SIGN_3_3 Sign bit of combined matrix constant Combined matrix constant C33 of RGB->YCbCr, contrast and brightness adjustment for secondary display. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-252 Proprietary...
  • Page 259 NOTE: Bits 0:6 of this field are hardwired to ZERO. D2COLOR_MATRIX_SIGN_3_4 Sign bit of combined matrix constant Combined matrix constant C34 of RGB->YCbCr, contrast and brightness adjustment for secondary display. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-253...

  • Page 260: Secondary Display Subsampling Registers

    1=subsample CrCb (RB) by using 2 tap average method 2=subsample CrCb (RB) by using 1 tap on even pixel 3=subsample CrCb (RB) by using 1 tap on odd pixel Sub-sampling control for secondary display. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-254 Proprietary...

  • Page 261: Secondary Display Hardware Cursor Registers

    D2CURSOR_X_POSITION 28:16 Secondary display hardware cursor X coordinate at the hot spot rela- tive to the desktop coordinates. Secondary display hardware cursor position © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-255...
  • Page 262 Secondary display hardware cursor update taken status. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0 D2CURSOR_UPDATE_LOCK Secondary display hardware cursor update lock control. 0=Unlocked 1=Locked M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-256 Proprietary...

  • Page 263: Secondary Display Hardware Icon Registers

    D2ICON_COLOR1 - RW - 32 bits - DISPDEC:0x6C58 Field Name Bits Default Description D2ICON_COLOR1_BLUE Secondary display hardware icon blue component of color 1. D2ICON_COLOR1_GREEN 15:8 Secondary display hardware icon green component of color 1. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-257...
  • Page 264 Secondary display hardware icon update Taken status. It is set to 1 when double buffering occurs and cleared when V_UPDATE = 0 D2ICON_UPDATE_LOCK Secondary display hardware icon update lock control. 0=Unlocked 1=Locked Secondary display hardware icon update control M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-258 Proprietary...

  • Page 265: Display Controller Look Up Table B Registers

    0=Green data is unsigned 1=Green data is signed DC_LUTB_DATA_G_FLOAT_POINT_EN Frame buffer green data float point enable for look-up table A. 0=Green data is fix point 1=Green data is float point © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-259...
  • Page 266 DC_LUTB_BLACK_OFFSET_RED - RW - 32 bits - DISPDEC:0x6CCC Field Name Bits Default Description DC_LUTB_BLACK_OFFSET_RED 15:0 Black value offset of red component for LUTB. Black value offset of red component for LUTB. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-260 Proprietary...
  • Page 267 DC_LUTB_WHITE_OFFSET_RED - RW - 32 bits - DISPDEC:0x6CD8 Field Name Bits Default Description DC_LUTB_WHITE_OFFSET_RED 15:0 0xffff White value offset of red component for LUTB White value offset of red component for LUTB © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-261...

  • Page 268: Display Controller Crc Registers

    DCP_CRC_P0_LAST - RW - 32 bits - DISPDEC:0x6C90 Field Name Bits Default Description DCP_CRC_P0_LAST (R) 31:0 Final value of CRC for previous frame pipe 0. Final value of CRC for previous frame pipe 0. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-262 Proprietary...
  • Page 269 DCP_CRC_P1_LAST - RW - 32 bits - DISPDEC:0x6C94 Field Name Bits Default Description DCP_CRC_P1_LAST (R) 31:0 Final value of CRC for previous frame pipe 1. Final value of CRC for previous frame pipe 1. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-263...

  • Page 270: Display/Memory Interface Control And Status Registers

    1=MH sends data to DMIF when there is no data pending request. DMIF_CLEAR_MC_SEND_ON_IDLE (W) This register bit is used to clear register DMIF_MH_SEND_ON_IDLE 0=No effect 1=Clear register bit DMIF_MH_SEND_ON_IDLE This is a debug register. DMIF status. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-264 Proprietary...

  • Page 271: Mcif Control Registers

    MCIF_BUFF_SIZE MCIF memory size. 0x0 - full memory size, 16x143bits. 0x1 - 3/4 memory size. 0x2 - 1/2 memory size. 0x3 - 1/4 memory size. MCIF control register © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-265...

  • Page 272: Display Controller To Line Buffer Control Registers

    1. The default value is 1. If any display has 32bpp digital output enabled, this values should be set to 4 DCP LB chunk gap control M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-266 Proprietary...

  • Page 273: Crtc Registers

    Cutoff H sync A at end of H BLANK when end of H sync A is beyond H BLANK 0 = cutoff is enabled 1 = cutoff is disabled Controls the H SYNC A for CRTC1 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-267...
  • Page 274 The last line of vertical blank is D1CRTC_V_BLANK_END - 1. Double-buffered with D1MODE_MASTER_UPDATE_LOCK Defines the vertical blank region of the display timing for CRTC1 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-268 Proprietary...
  • Page 275 D1CRTC_V_SYNC_B_CNTL - RW - 32 bits - DISPDEC:0x6034 Field Name Bits Default Description D1CRTC_V_SYNC_B_POL Controls polarity of vertical sync B 0 = active high 1 = active low Controls vertical sync B for CRTC1 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-269...
  • Page 276 D1CRTC_TRIGA_CLEAR (W) Clears the sticky bit D1CRTC_TRIGA_OCCURRED when written with '1' Controls for external trigger A signal in CRTC1 D1CRTC_TRIGA_MANUAL_TRIG - RW - 32 bits - DISPDEC:0x6064 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-270 Proprietary...
  • Page 277 11 = send every 4 signals D1CRTC_TRIGB_DELAY 28:24 A programmable delay to send external trigger B signal D1CRTC_TRIGB_CLEAR (W) Clears the sticky bit D1CRTC_TRIGB_OCCURRED when written with '1' © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-271...
  • Page 278 0 = output of source mux of flow control signal is low 1 = output of source mux of flow control signal is high Controls flow control of CRTC1 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-272...
  • Page 279 D1CRTC_BLANK_CONTROL - RW - 32 bits - DISPDEC:0x6084 Field Name Bits Default Description D1CRTC_CURRENT_BLANK_STATE (R) Read only status indicating current state of display blanking. 0 = screen not blanked 1 = screen is blanked © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-273...
  • Page 280 Bits Default Description D1CRTC_OVERSCAN_COLOR_BLUE B or Cb component D1CRTC_OVERSCAN_COLOR_GREEN 19:10 G or Y component D1CRTC_OVERSCAN_COLOR_RED 29:20 R or Cr component Defines color of the overscan region for CRTC1 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-274 Proprietary...
  • Page 281 D1CRTC_STATUS_FRAME_COUNT - RW - 32 bits - DISPDEC:0x60A4 Field Name Bits Default Description D1CRTC_FRAME_COUNT (R) 23:0 Reports current frame count Current frame count for CRTC1 D1CRTC_STATUS_VF_COUNT - RW - 32 bits - DISPDEC:0x60A8 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-275...
  • Page 282 01 = force VSYNC next line on CRTC trigger A signal 10 = force VSYNC next line on CRTC trigger B signal 11 = reserved Controls the feature to force VSYNC next line for CRTC1 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-276 Proprietary...
  • Page 283 Enables toggling of STEREOSYNC and STEREO_SELECT signals 0 = disable toggling. 1 = enable toggling at every frame (progressive) or every field (inter- lace) at leading edge of VSYNCA Stereosync control for CRTC1 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-277...
  • Page 284 Interrupt mask for CRTC snapshot event 0 = disables interrupt 1 = enables interrupt D1CRTC_FORCE_COUNT_NOW_INT_MSK Interrupt mask for force count now event 0 = disables interrupt 1 = enables interrupt M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-278 Proprietary...
  • Page 285 0 = no lock, double buffering can occur 1 = set lock to prevent double buffering Update lock for CRTC1 timing registers D1CRTC_DOUBLE_BUFFER_CONTROL - RW - 32 bits - DISPDEC:0x60EC Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-279...
  • Page 286 E.g. for 800 pixels set to 799 = 0x31F Double-buffered with D2MODE_MASTER_UPDATE_LOCK Defines horizontal dimension of the display timing for CRTC2 D2CRTC_H_BLANK_START_END - RW - 32 bits - DISPDEC:0x6804 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-280 Proprietary...
  • Page 287 B Defines the position of horizontal sync B for CRTC2 D2CRTC_H_SYNC_B_CNTL - RW - 32 bits - DISPDEC:0x6814 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-281...
  • Page 288 Field Name Bits Default Description D2CRTC_V_SYNC_A_POL Polarity of V SYNC A 0 = active high 1 = active low Double-buffered with D2MODE_MASTER_UPDATE_LOCK Controls V SYNC A for CRTC2 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-282 Proprietary...
  • Page 289 D2CRTC_TRIGA_INPUT_STATUS (R) Read back the value of the external trigger A input signal after the D2CRTC_TRIGA_POLARITY_STATUS (R) Reports the value of the external trigger A polarity signal after the © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-283...
  • Page 290 Field Name Bits Default Description D2CRTC_TRIGA_MANUAL_TRIG (W) One shot trigger for external trigger A signal when written with '1' Manual trigger for external trigger A signal of CRTC2 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-284 Proprietary...
  • Page 291 A programmable delay to send external trigger B signal D2CRTC_TRIGB_CLEAR (W) Clears the sticky bit D2CRTC_TRIGB_OCCURRED when written with '1' Control for external trigger B signal of CRTC2 D2CRTC_TRIGB_MANUAL_TRIG - RW - 32 bits - DISPDEC:0x686C © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-285...
  • Page 292 1 = output of source mux of flow control signal is high Controls flow control of CRTC2 D2CRTC_PIXEL_DATA_READBACK - RW - 32 bits - DISPDEC:0x6878 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-286 Proprietary...
  • Page 293 D2CRTC_BLANK_CONTROL - RW - 32 bits - DISPDEC:0x6884 Field Name Bits Default Description D2CRTC_CURRENT_BLANK_STATE (R) Read only status indicating current state of display blanking. 0 = screen not blanked 1 = screen is blanked © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-287...
  • Page 294 D2CRTC_OVERSCAN_COLOR - RW - 32 bits - DISPDEC:0x6894 Field Name Bits Default Description D2CRTC_OVERSCAN_COLOR_BLUE B or Cb component D2CRTC_OVERSCAN_COLOR_GREEN 19:10 G or Y component D2CRTC_OVERSCAN_COLOR_RED 29:20 R or Cr component M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-288 Proprietary...
  • Page 295 D2CRTC_STATUS_POSITION - RW - 32 bits - DISPDEC:0x68A0 Field Name Bits Default Description D2CRTC_VERT_COUNT (R) 12:0 Reports current vertical count D2CRTC_HORZ_COUNT (R) 28:16 Reports current horizontal count Current horizontal and vertical count of CRTC2 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-289...
  • Page 296 Bits Default Description D2CRTC_FORCE_VSYNC_NEXT_LINE_OCCU Reports whether force vsync next line event has occurred. Sticky bit. RRED (R) 0 = event has not occurred 1 = event has occurred M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-290 Proprietary...
  • Page 297 1 = snapshot has occurred D2CRTC_SNAPSHOT_CLEAR (W) Clears the D2CRTC_SNAPSHOT_OCCURRED sticky bit when writ- ten with '1' D2CRTC_SNAPSHOT_MANUAL_TRIGGER (W) One shot trigger to perform snapshot when written with '1' Controls CRTC2 snapshot © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-291...
  • Page 298 0 = disables interrupt 1 = enables interrupt D2CRTC_TRIGB_INT_MSK Interrupt mask for CRTC external trigger B 0 = disables interrupt 1 = enables interrupt Interrupt mask for CRTC2 events M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-292 Proprietary...
  • Page 299 Enables the double buffering of D2CRTC_BLANK_DATA_EN 0 = disables double buffering. D2CRTC_BLANK_DATA_EN is updated immediately 1 = enables double buffering of D2CRTC_BLANK_DATA_EN when V_UPDATE is active Controls double buffering of CRTC2 registers © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-293...
  • Page 300 0: CRTC2 will continuously latch in timing parameters from VGA 1: CRTC2 will continuously latch in timing parameters from VGA except during VGA parameter recalculated window Controls how VGA timing parameters are captured M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-294 Proprietary...

  • Page 301: Display Output Registers

    19:10 0x3ff Mask bits for DACA G channel CRC DACA_CRC_SIG_RED_MASK 29:20 0x3ff Mask bits for DACA R channel CRC Mask bits for R, G & B CRC calculations © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-295...
  • Page 302 0=DACA uses HSYNC_A & VSYNC_A 1=DACA used HSYNC_B & VSYNC_B DACA_STEREOSYNC_SELECT 0: selects crtc1 stereosync 1: selects crtc2 stereosync 0=DACA uses CRTC1 STEREOSYNC 1=DACA uses CRTC2 STEREOSYNC DACA ...SYNC selection M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-296 Proprietary...
  • Page 303 2: Channel is not checked 3: Reserved DACA_AUTODETECT_BLUE_SENSE (R) 25:24 Two bit result from last Blue/Comp compare: 0: Channel is disconnected 1: Channel is connected 2: Channel is not checked 3: Reserved © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-297...
  • Page 304 0x3 HDTV (Component Video) DACA_WHITE_FINE_CONTROL 12:8 0x10 Full-scale Output Adjustment - DACADJ(4:0) DACA_BANDGAP_ADJUSTMENT 19:16 Bandgap Reference Voltage Adjustment - BGADJ(3:0) DACA_ANALOG_MONITOR 27:24 Analog test mux select - MON(3:0) M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-298 Proprietary...
  • Page 305 DAC G_ASYNC_EN pin. 0=Disable 1=Enable DACA_B_ASYNC_ENABLE DACA blue channel asynchronous mode enable.Used in conjunction with core logic to drive the DAC B_ASYNC_EN pin. 0=Disable 1=Enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-299...
  • Page 306 DACB_SOURCE_SELECT - RW - 32 bits - DISPDEC:0x7A04 Field Name Bits Default Description DACB_SOURCE_SELECT 0=Source is CRTC1 1=Source is CRTC2 2=Source is TV Encoder 3=Reserved Select between 1st display, 2nd display & TV encoder streams M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-300 Proprietary...
  • Page 307 DACB_CRC_SIG_GREEN (R) 19:10 0x3ff CRC signature value for DACB green component DACB_CRC_SIG_RED (R) 29:20 0x3ff CRC signature value for DACB red component DACB CRC R, G & B results © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-301...
  • Page 308 DACB macro Bandgap voltage reference power up time. Default = 11 microseconds. DACB_AUTODETECT_TESTMODE 0: Normal operation 1: Test mode - count in 1us units DACB_AUTODETECT_STATUS - RW - 32 bits - DISPDEC:0x7A34 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-302 Proprietary...
  • Page 309 1=Enable Data Force Control DACB_FORCE_DATA - RW - 32 bits - DISPDEC:0x7A40 Field Name Bits Default Description DACB_FORCE_DATA Data to be forced on R, G & B channels © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-303...
  • Page 310 TV_ENABLE=0, Y/C/Comp when TV_ENABLE=1. Drives DAC TVENABLE input. DACB_ZSCALE_SHIFT DACB zero scale shift enable. Causes DAC to add a small offset to the levels of all outputs. Drives DAC ZSCALE_SHIFT pin. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-304 Proprietary...
  • Page 311 DACB red channel comparator output value comes from DAC RDAC- DET pin DACB_TEST_ENABLE - RW - 32 bits - DISPDEC:0x7A64 Field Name Bits Default Description DACB_TEST_ENABLE 0=Disable 1=Enable DACBTEST Enable. Use for DAC test only. Drives DAC © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-305...
  • Page 312 Select between CRTC1 and CRTC2 stereosync signals 0=CRTC1 STEREOSYNC used 1=CRTC2 STEREOSYNC used Source Select control for Data, H/VSYNC & Stereosync TMDSA_COLOR_FORMAT - RW - 32 bits - DISPDEC:0x7888 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-306 Proprietary...
  • Page 313 TMDSA_TEMPORAL_DITHER_DEPTH Controls bits per pixel 0=18bpp 1=24bpp TMDSA_TEMPORAL_LEVEL Gray level select (2 or 4 levels) 0=Gray level 2(1 bit - LSB) 1=Gray level 4(2 bits - 2 LSBs) © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-307...
  • Page 314 TMDSA SYNC character set 1 TMDSA_SYNC_CHAR_PATTERN_2_3 - RW - 32 bits - DISPDEC:0x78AC Field Name Bits Default Description TMDSA_SYNC_CHAR_PATTERN2 TMDSA SYNC character set 2 TMDSA_SYNC_CHAR_PATTERN3 25:16 TMDSA SYNC character set 3 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-308 Proprietary...
  • Page 315 TMDSA_CRC_SIG_CONTROL (R) 26:24 CRC signature value for TMDSA control signals3-bit input value: bit 2 = Vsync bit 1 = Hsync bit 0 =Data Enable RGB and Control CRC Result © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-309...
  • Page 316 Set to 1 to enable debug mode TMDSA_DEBUG_HSYNC Debug mode HSYNC TMDSA_DEBUG_HSYNC_EN Set to 1 to enable debug mode HSYNC TMDSA_DEBUG_VSYNC Debug mode VSYNC TMDSA_DEBUG_VSYNC_EN Set to 1 to enable debug mode VSYNC M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-310 Proprietary...
  • Page 317 PCLK_TMDSA or PCLK_TMDSA_DIRECT (IDCLK) is repro- grammed or stopped and restarted. TMDSA Data Sychronization Control TMDSA_CTL0_1_GEN_CNTL - RW - 32 bits - DISPDEC:0x78DC Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-311...
  • Page 318 Select CTL1 output data 0=Register value 1=Pattern generator output TMDSA_2BIT_COUNTER_EN Set to 1 to enable 2-bit data modulation counter 0=Disable 1=Enable TMDSA_CTL2_3_GEN_CNTL - RW - 32 bits - DISPDEC:0x78E0 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-312 Proprietary...
  • Page 319 Set to 1 to force continunous toggle on CTL3 internal feedback path TMDSA_CTL3_PATTERN_OUT_EN Select CTL3 output data 0=Register value 1=Pattern generator output TMDSA_TRANSMITTER_ENABLE - RW - 32 bits - DISPDEC:0x7904 Field Name Bits Default Description © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-313...
  • Page 320 TMDSA_PLL_DUTY_CYCLE 17:16 TMDSA PLL duty cycle control. Go to IPPLDC(2:0) pins of TMDSA macro. TMDSA_TX_VOLTAGE_SWING 23:20 TMDSA driver voltage swing control. Go to IPTXVS(3:0) pins of TMDSA macro. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-314 Proprietary...
  • Page 321 TMDSA_TEST_CNTL 18:16 Selects which of six register test output channels from TMDSA macro is visible in TMDSA_REG_TEST_OUTPUT. 0=OTDAT0 1=OTDAT1 2=OTDAT2 3=OTDAT3 4=OTDAT4 5=OTDAT5 6=OTDAT0 7=OTDAT0 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-315...
  • Page 322 Enable bit reduction by spatial (random) dither 0=Disable 1=Enable DVOA_SPATIAL_DITHER_DEPTH Select spatial dither depth 0=18bpp 1=24bpp DVOA_TEMPORAL_DITHER_EN Enable bit reduction by temporal dither (frame mod.) 0=Disable 1=Enable DVOA_TEMPORAL_DITHER_DEPTH Select temporal dither depth 0=18bpp 1=24bpp M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-316 Proprietary...
  • Page 323 DVOA_CRC_CONT_EN Select between one shot and continuous mode 0=CRC is calculated over 1 frame 1=CRC is continuously calculated for every frame DVOA_CRC2_EN Enable DVO output CRC2 0=Disable 1=Enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-317...
  • Page 324 1=Odd field begins CRC calculation DVOA_CRC_ONLY_BLANKb Determines whether CRC is calculated for the whole frame or only during non-blank period for DVO 0=CRC calculated over entire field 1=CRC calculated only during BLANKb M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-318 Proprietary...
  • Page 325 Field Name Bits Default Description DVOA_CRC2_SIG_RESULT (R) 26:0 CRC2 signature value for DVO output CRC2 signature value for DVO output DVOA_STRENGTH_CONTROL - RW - 32 bits - DISPDEC:0x79B4 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-319...
  • Page 326 Description DC_HOT_PLUG_DETECT1_EN Enable 1st HPD circuit When disabled, HPD interrupts will not happen and DC_HOT_PLUG_DETECT1_SENSE will not change 0=Disable 1=Enable DC_HOT_PLUG_DETECT1_INT_STATUS - RW - 32 bits - DISPDEC:0x7D04 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-320 Proprietary...
  • Page 327 Interrupt acknowledge for the 2nd HPD circuit DC_HOT_PLUG_DETECT2_INT_POLARITY Polarity of 2nd HPD circuit. 0=generate interrupt on disconnect 1=generate interrupt on connect DC_HOT_PLUG_DETECT2_INT_EN Enable Interrupts on the 2nd HPD circuit 0=Disable 1=Enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-321...
  • Page 328 Select DDC pins to be used by DOUT I2C master 0=DOUT I2C Master uses DDC1_DATA and DDC1_CLK pins 1=DOUT I2C Master uses DDC2_DATA and DDC2_CLK pins 2=DOUT I2C Master uses DDC3_DATA and DDC3_CLK pins 3=Reserved M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-322 Proprietary...
  • Page 329 DC_I2C_ARBITRATION - RW - 32 bits - DISPDEC:0x7D50 Field Name Bits Default Description DC_I2C_SW_WANTS_TO_USE_I2C (W) Asserted when HOST wants to use DOUT I2C 0=No effect 1=SW requests to use DOUT I2C interface © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-323...
  • Page 330 12=GENERICA test debug clock from SCG 13=Reserved 14=Reserved 15=Reserved DC_GENERICB - RW - 32 bits - DISPDEC:0x7DC4 Field Name Bits Default Description GENERICB_EN Enable signals for GENERICB pad M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-324 Proprietary...
  • Page 331 1=PPLL1 Reference Clock Output 2=PPLL2 Reference Clock Output 3=Reserved HSYNCB_OUTPUT_SEL 0=Reference Clock Output disabled 1=PPLL1 Reference Clock Output 2=PPLL2 Reference Clock Output 3=Reserved Control output of external reference clocks © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-325...
  • Page 332 DC_GPIO_VIP_DEBUG - RW - 32 bits - DISPDEC:0x7E2C Field Name Bits Default Description DC_GPIO_VIP_DEBUG Control whether display or VIP controls DVODATA[23:16] and DVOCNTL[2] 0: VIP / test/debug bus control pads 1: display controls pads M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-326 Proprietary...
  • Page 333 Default Description DC_GPIO_DVODATA_Y (R) 23:0 Values on DVODATA pads. DC_GPIO_DVOCNTL_Y (R) 26:24 Values on DVOCNTL pads. DC_GPIO_DVOCLK_Y (R) Values on DVOCLK pads. Output values of the DVO pads. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-327...
  • Page 334 Pad values generated by hardware are overridden. Control GPIO functionality of the DDC2 pads - all fields are active high. DC_GPIO_DDC2_A - RW - 32 bits - DISPDEC:0x7E54 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-328 Proprietary...
  • Page 335 DC_GPIO_DDC3CLK_MASK = 1. DC_GPIO_DDC3DATA_A Asynchronous input for DDC3DATA when DC_GPIO_DDC3DATA_MASK = 1. Asynchronous inputs for the DDC3 pads when the GPIO functionality is enabled by the DC_GPIO_DDC3_MASK register. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-329...
  • Page 336 DC_GPIO_VSYNCA_EN Output enable for VSYNCA when DC_GPIO_VSYNCA_MASK = 1. Output enable values for the HSYNCA & VSYNCA pads when the GPIO functionality is enabled by the DC_GPIO_SYNCA_MASK register. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-330 Proprietary...
  • Page 337 Enable/Disable GPIO functionality on HPD1 pad 0=Pad Driven by Hardware - Normal Operation 1=Pad Controlled by Software through associated GPIO registers. Pad values generated by hardware are overridden. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-331...
  • Page 338 Asynchronous inputs for the BLON & DIGON pads when the GPIO functionality is enabled by the DC_GPIO_PWRSEQ_MASK register. DC_GPIO_PWRSEQ_EN - RW - 32 bits - DISPDEC:0x7EA8 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-332 Proprietary...
  • Page 339 LVTMA_CAPTURE_START_AK (W) 00 - No effect 01 - Clear Capture_start DVOA_CAPTURE_START_AK (W) Acknowledge bit for DVOA Capture Start. This bit will clear DVOA_CAPTURE_START and DISP_INTERRUPT_STATUS.DVOA_CAPTURE_START_INTERRU 0=No effect 1=Clear Capture_start © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-333...
  • Page 340 Control SN strengths for BLON & DIGON pads PWRSEQ_STRENGTH_SP 23:20 Control SP strengths for BLON & DIGON pads DISP_INTERRUPT_STATUS - RW - 32 bits - DISPDEC:0x7EDC Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-334 Proprietary...
  • Page 341 TRIGA event has occurred. CRTC2_TRIGB_INTERRUPT (R) Interrupt that can be generated by the secondary display controller when it detects a secondary TRIGB event has occurred. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-335...
  • Page 342 1=When in WAIT_PPLL_ON, wait for 1 ms proceeding to next state PWRUP_WAIT_MEM_INIT_DONE Control whether power management mem_init_done indicator 0=When in WAIT_MEM_INIT_DONE, proceed to next state 1=When in WAIT_MEM_INIT_DONE, wait for mem_init_done indi- cator M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-336 Proprietary...
  • Page 343 This bit equals the display timer status (DISP_TIMER_INT_STAT) logically 'AND'ed with the display timer interrupt mask (DISP_TIMER_INT_MSK). Display Countdown Timer capable of generating a hardware interrupt © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-337...

  • Page 344: Display Output Miscellaneous Registers

    Description DO_PERFCOUNTER1_LOW (R) 31:0 Readback of the low order bits of the second performance counter DCO_PERFMON_CNTL_R - RW - 32 bits - DISPDEC:0x7F18 Field Name Bits Default Description M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-338 Proprietary...
  • Page 345 1=VGA interrupt has occurred General Interrupt Status register. These fields can be polled and acknowledged even if interrupts are disabled, or the respective fields are masked in the GEN_INT_CNTL register. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-339...

  • Page 346: Lvds Registers

    1=HSYNC_B & VSYNC_B from the selected CRTC are used LVTMA_STEREOSYNC_SELECT Select between CRTC1 and CRTC2 stereosync signals 0=CRTC1 STEREOSYNC used 1=CRTC2 STEREOSYNC used Source Select control for Data, H/VSYNC & Stereosync M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-340 Proprietary...
  • Page 347 Enable bit reduction by spatial (random) dither 0=Disable 1=Enable LVTMA_SPATIAL_DITHER_DEPTH Controls reduction depth 0=18bpp 1=24bpp LVTMA_TEMPORAL_DITHER_EN Enable bit reduction by temporal dither (frame mod.) 0=Disable 1=Enable LVTMA_TEMPORAL_DITHER_DEPTH Controls dither Depth 0=18bpp 1=24bpp © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-341...
  • Page 348 LVTMA_SYNC_CHAR_PATTERN_0_1 - RW - 32 bits - DISPDEC:0x7AA8 Field Name Bits Default Description LVTMA_SYNC_CHAR_PATTERN0 LVTMA SYNC character set 0 LVTMA_SYNC_CHAR_PATTERN1 25:16 LVTMA SYNC character set 1 LVTMA_SYNC_CHAR_PATTERN_2_3 - RW - 32 bits - DISPDEC:0x7AAC M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-342 Proprietary...
  • Page 349 26:24 CRC mask bits for LVTMA control signals 3-bit input value: bit 2 = Vsync bit 1 = Hsync bit 0 =Data Enable RGB and Control CRC Mask © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-343...
  • Page 350 1=External signal resets random and half clock patterns LVTMA_LVDS_EYE_PATTERN Controls between normal output and LVDS eye pattern 0=Normal 1=Replace data with eye pattern LVTMA_STATIC_TEST_PATTERN 25:16 LVTMA test pixel. Replace the pixel value when LVTMA_TEST_PATTERN_OUT_EN=1 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-344 Proprietary...
  • Page 351 DC Balancer select value to use when DCBALANCER_EN=0 LVTMA_RED_BLUE_SWITCH - RW - 32 bits - DISPDEC:0x7AD4 Field Name Bits Default Description LVTMA_RB_SWITCH_EN Switch Red and Blue encoding position. 0=Disable 1=Enable © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-345...
  • Page 352 4=CTL1 data is delayed 4 pixel clocks 5=CTL1 data is delayed 5 pixel clocks 6=CTL1 data is delayed 6 pixel clocks 7=CTL1 data is delayed 7 pixel clocks M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-346 Proprietary...
  • Page 353 1=Pattern generator output LVTMA_CTL3_DATA_SEL 19:16 Select data to be used to generate CTL3 pattern (selected fields are ORed together) [0]: Display Enable [1]: VSYNC [2]: HSYNC [3] Always (blank time) © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-347...
  • Page 354 DIGON disable during power down LVTMA_PWRSEQ_DELAY2 - RW - 32 bits - DISPDEC:0x7AEC Field Name Bits Default Description LVTMA_PWRDN_MIN_LENGTH Number of LVTMA_PWRSEQ_REF pulses to delay from completion of powerdown to powerup M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-348 Proprietary...
  • Page 355 LVTMA_BLON LVDS backlight voltage 0:off 1:on LVTMA_BLON_OVRD Enable override of power sequencer BLON (before modulation) by register value 0=Disable 1=Enable LVTMA_BLON_POL Polarity of output BLON signal 0=Non-invert 1=Invert © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-349...
  • Page 356 Determines duty cycle of BLON signal duty cycle = BL_MOD_LEVEL/256 LVTMA_LVDS_DATA_CNTL - RW - 32 bits - DISPDEC:0x7AFC Field Name Bits Default Description LVTMA_LVDS_24BIT_ENABLE Enable 4th data channel for 24-bit output 0=Disable 1=Enable M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-350 Proprietary...
  • Page 357 LVTMA link1 data channel 0 enable (ICH5EN)(set to 1 when LVTM is enabled and in dual-link mode) LVTMA_LNKD11EN LVTMA link1 data channel 1 enable (ICH6EN)(set to 1 when LVTM is enabled and in dual-link mode) © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-351...
  • Page 358 LVTMA transmitter PLL enable. 0=LVTMA Transmitter PLL is disabled 1=LVTMA Transmitter PLL is enabled LVTMA_PLL_RESET LVTMA transmitter PLL reset. PLL will start the locking acquisition process once this becomes low. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-352 Proprietary...
  • Page 359 See macro spec for recommended settings in TMDS and LVDS modes 0=0: Use serialized data (LVTMA_CLK_PATTERN) as clock 1=1: Use clock selected by LVTMA_BYPASS_PLL (ICHCSEL1) LVTMA_INPUT_TEST_CLK_SEL Controls ITCLKSEL pin on LVTM macro © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary 2-353...
  • Page 360 Drives ITPL pins on LVTMA macro (this functionality doesn't exist - pins are unconnected) LVTMA_TX_DEBUG 11:8 Drives ITX pins on LVTMA macro (this functionality doesn't exist ? pins are unconnected) Reserved for debugging purposes M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. 2-354 Proprietary...
  • Page 361 “VGA CRT Registers Sorted By Name” on page A-66 “VGA GRPH Registers Sorted By Name” on page A-67 “VGA SEQ Registers Sorted By Name” on page A-68 “All Registers Sorted by Name” on page A-69 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...

  • Page 362: Configuration Registers Sorted By Name

    2-76 F1_PMI_PMC_REG CFGF1_DEC:0x52 HIDEC:0x5452 2-76 F1_PMI_STATUS CFGF1_DEC:0x54 HIDEC:0x5454 2-77 F1_REG_BASE_HI CFGF1_DEC:0x14 HIDEC:0x541C 2-75 F1_REG_BASE_LO CFGF1_DEC:0x10 HIDEC:0x5414 2-75 F1_REGPROG_INF CFGF1_DEC:0x9 HIDEC:0x5409 2-74 F1_REVISION_ID CFGF1_DEC:0x8 HIDEC:0x5408 2-73 F1_STATUS CFGF1_DEC:0x6 HIDEC:0x5406 2-73 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 363 2-65 PMI_PMC_REG CFGF0_DEC:0x52 HIDEC:0x5052 2-66 PMI_STATUS CFGF0_DEC:0x54 HIDEC:0x5054 2-66 REG_BASE_HI CFGF0_DEC:0x1C HIDEC:0x501C 2-64 REG_BASE_LO CFGF0_DEC:0x18 HIDEC:0x5018 2-63 REGPROG_INF CFGF0_DEC:0x9 HIDEC:0x5009 2-62 REVISION_ID CFGF0_DEC:0x8 HIDEC:0x5008 2-62 STATUS CFGF0_DEC:0x6 HIDEC:0x5006 2-61 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...
  • Page 364 Table A-1 Configuration Registers Sorted by Name (Continued) Register Name Address Secondary Address Page SUB_CLASS CFGF0_DEC:0xA HIDEC:0x500A 2-62 VENDOR_ID CFGF0_DEC:0x0 HIDEC:0x5000 2-60 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...

  • Page 365: Configuration Registers Sorted By Address

    2-67 STATUS CFGF0_DEC:0x6 HIDEC:0x5006 2-61 DEVICE_CNTL CFGF0_DEC:0x60 HIDEC:0x5060 2-67 DEVICE_STATUS CFGF0_DEC:0x62 HIDEC:0x5062 2-68 LINK_CAP CFGF0_DEC:0x64 HIDEC:0x5064 2-68 LINK_CNTL CFGF0_DEC:0x68 HIDEC:0x5068 2-68 LINK_STATUS CFGF0_DEC:0x6A HIDEC:0x506A 2-69 REVISION_ID CFGF0_DEC:0x8 HIDEC:0x5008 2-62 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...
  • Page 366 2-79 F1_LINK_STATUS CFGF1_DEC:0x6A HIDEC:0x546A 2-79 F1_REVISION_ID CFGF1_DEC:0x8 HIDEC:0x5408 2-73 F1_REGPROG_INF CFGF1_DEC:0x9 HIDEC:0x5409 2-74 F1_SUB_CLASS CFGF1_DEC:0xA HIDEC:0x540A 2-74 F1_BASE_CODE CFGF1_DEC:0xB HIDEC:0x540B 2-74 F1_CACHE_LINE CFGF1_DEC:0xC HIDEC:0x540C 2-74 F1_LATENCY CFGF1_DEC:0xD HIDEC:0x540D 2-74 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...
  • Page 367 Table A-2 Configuration Registers Sorted by Address (Continued) Register Name Address Secondary Address Page F1_HEADER CFGF1_DEC:0xE HIDEC:0x540E 2-74 F1_BIST CFGF1_DEC:0xF HIDEC:0x540F 2-75 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...

  • Page 368: Clock Registers Sorted By Name

    CLKIND:0x2A 2-163 SCLK_PWRMGT_CNTL CLKIND:0x9 2-157 SPLL_BYPASSCLK_SEL CLKIND:0x1 2-156 SPLL_CLK_SEL CLKIND:0x3 2-156 SPLL_CNTL_MODE CLKIND:0x2 2-156 SPLL_FUNC_CNTL CLKIND:0x0 2-155 SPLL_TIME CLKIND:0x24 2-162 TCL_DYN_CNTL CLKIND:0x1A 2-160 VIP_DYN_CNTL CLKIND:0x14 2-160 VOL_DROP_CNT CLKIND:0x36 2-164 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...

  • Page 369: Clock Registers Sorted By Address

    CLKIND:0x5 2-157 MPLL_CNTL_MODE CLKIND:0x6 2-157 MPLL_CLK_SEL CLKIND:0x7 2-157 GENERAL_PWRMGT CLKIND:0x8 2-157 SCLK_PWRMGT_CNTL CLKIND:0x9 2-157 MCLK_PWRMGT_CNTL CLKIND:0xA 2-158 DYN_PWRMGT_SCLK_CNTL CLKIND:0xB 2-158 DYN_PWRMGT_SCLK_LENGTH CLKIND:0xC 2-159 DYN_SCLK_PWMEN_PIPE CLKIND:0xD 2-159 DYN_SCLK_VOL_CNTL CLKIND:0xE 2-159 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...

  • Page 370: Display Registers Stored By Name

    2-276 D1CRTC_COUNT_RESET DISPDEC:0x60B0 2-276 D1CRTC_DOUBLE_BUFFER_CONTROL DISPDEC:0x60EC 2-280 D1CRTC_FLOW_CONTROL DISPDEC:0x6074 2-272 D1CRTC_FORCE_COUNT_NOW_CNTL DISPDEC:0x6070 2-272 D1CRTC_H_BLANK_START_END DISPDEC:0x6004 2-267 D1CRTC_H_SYNC_A DISPDEC:0x6008 2-267 D1CRTC_H_SYNC_A_CNTL DISPDEC:0x600C 2-267 D1CRTC_H_SYNC_B DISPDEC:0x6010 2-268 D1CRTC_H_SYNC_B_CNTL DISPDEC:0x6014 2-268 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-10 Proprietary...
  • Page 371 2-268 D1CRTC_VERT_SYNC_CONTROL DISPDEC:0x60BC 2-277 D1CRTC_VGA_PARAMETER_CAPTURE_MODE DISPDEC:0x60F0 2-280 D1CUR_COLOR1 DISPDEC:0x641C 2-223 D1CUR_COLOR2 DISPDEC:0x6420 2-223 D1CUR_CONTROL DISPDEC:0x6400 2-222 D1CUR_HOT_SPOT DISPDEC:0x6418 2-223 D1CUR_POSITION DISPDEC:0x6414 2-222 D1CUR_SIZE DISPDEC:0x6410 2-222 D1CUR_SURFACE_ADDRESS DISPDEC:0x6408 2-222 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-11...
  • Page 372 2-279 D1OVL_ALPHA DISPDEC:0x6308 2-213 D1OVL_ALPHA_CONTROL DISPDEC:0x630C 2-214 D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL DISPDEC:0x6140 2-217 D1OVL_CONTROL1 DISPDEC:0x6184 2-203 D1OVL_CONTROL2 DISPDEC:0x6188 2-203 D1OVL_ENABLE DISPDEC:0x6180 2-203 D1OVL_END DISPDEC:0x61A8 2-205 D1OVL_KEY_ALPHA DISPDEC:0x632C 2-216 D1OVL_KEY_CONTROL DISPDEC:0x6300 2-213 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-12 Proprietary...
  • Page 373 2-212 D1OVL_PWL_3C0TO3FF DISPDEC:0x62C8 2-212 D1OVL_PWL_40TO7F DISPDEC:0x6290 2-209 D1OVL_PWL_80TOBF DISPDEC:0x6294 2-210 D1OVL_PWL_C0TOFF DISPDEC:0x6298 2-210 D1OVL_PWL_TRANSFORM_EN DISPDEC:0x6280 2-209 D1OVL_START DISPDEC:0x61A4 2-204 D1OVL_SURFACE_ADDRESS DISPDEC:0x6190 2-204 D1OVL_SURFACE_ADDRESS_INUSE DISPDEC:0x61B0 2-205 D1OVL_SURFACE_OFFSET_X DISPDEC:0x619C 2-204 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-13...
  • Page 374 2-280 D2CRTC_INTERLACE_CONTROL DISPDEC:0x6888 2-288 D2CRTC_INTERLACE_STATUS DISPDEC:0x688C 2-288 D2CRTC_INTERRUPT_CONTROL DISPDEC:0x68DC 2-292 D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE DISPDEC:0x68B8 2-290 D2CRTC_OVERSCAN_COLOR DISPDEC:0x6894 2-288 D2CRTC_PIXEL_DATA_READBACK DISPDEC:0x6878 2-287 D2CRTC_SNAPSHOT_CONTROL DISPDEC:0x68CC 2-292 D2CRTC_SNAPSHOT_FRAME DISPDEC:0x68D4 2-292 D2CRTC_SNAPSHOT_POSITION DISPDEC:0x68D0 2-292 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-14 Proprietary...
  • Page 375 2-256 D2GRPH_ALPHA DISPDEC:0x6B04 2-246 D2GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL DISPDEC:0x6B80 2-250 D2GRPH_CONTROL DISPDEC:0x6904 2-231 D2GRPH_ENABLE DISPDEC:0x6900 2-231 D2GRPH_FLIP_CONTROL DISPDEC:0x6948 2-235 D2GRPH_KEY_RANGE_ALPHA DISPDEC:0x6B1C 2-248 D2GRPH_KEY_RANGE_BLUE DISPDEC:0x6B18 2-248 D2GRPH_KEY_RANGE_GREEN DISPDEC:0x6B14 2-247 D2GRPH_KEY_RANGE_RED DISPDEC:0x6B10 2-247 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-15...
  • Page 376 2-248 D2OVL_KEY_RANGE_GREEN_Y DISPDEC:0x6B24 2-248 D2OVL_KEY_RANGE_RED_CR DISPDEC:0x6B20 2-248 D2OVL_MATRIX_COEF_1_1 DISPDEC:0x6A04 2-239 D2OVL_MATRIX_COEF_1_2 DISPDEC:0x6A08 2-239 D2OVL_MATRIX_COEF_1_3 DISPDEC:0x6A0C 2-239 D2OVL_MATRIX_COEF_1_4 DISPDEC:0x6A10 2-239 D2OVL_MATRIX_COEF_2_1 DISPDEC:0x6A14 2-240 D2OVL_MATRIX_COEF_2_2 DISPDEC:0x6A18 2-240 D2OVL_MATRIX_COEF_2_3 DISPDEC:0x6A1C 2-240 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-16 Proprietary...
  • Page 377 2-237 D2OVL_UPDATE DISPDEC:0x69AC 2-238 D2VGA_CONTROL DISPDEC:0x338 2-190 DAC_DATA DISPDEC:0x3C9 2-168 DAC_MASK DISPDEC:0x3C6 2-168 DAC_R_INDEX DISPDEC:0x3C7 2-168 DAC_W_INDEX DISPDEC:0x3C8 2-168 DACA_AUTODETECT_CONTROL DISPDEC:0x7828 2-297 DACA_AUTODETECT_CONTROL2 DISPDEC:0x782C 2-297 DACA_AUTODETECT_INT_CONTROL DISPDEC:0x7838 2-298 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-17...
  • Page 378 2-302 DACB_CRC_SIG_CONTROL_MASK DISPDEC:0x7A14 2-301 DACB_CRC_SIG_RGB DISPDEC:0x7A18 2-301 DACB_CRC_SIG_RGB_MASK DISPDEC:0x7A10 2-301 DACB_ENABLE DISPDEC:0x7A00 2-300 DACB_FORCE_DATA DISPDEC:0x7A40 2-304 DACB_FORCE_OUTPUT_CNTL DISPDEC:0x7A3C 2-303 DACB_POWERDOWN DISPDEC:0x7A50 2-304 DACB_PWR_CNTL DISPDEC:0x7A68 2-306 DACB_SOURCE_SELECT DISPDEC:0x7A04 2-300 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-18 Proprietary...
  • Page 379 2-332 DC_GPIO_PAD_STRENGTH_1 DISPDEC:0x7ED4 2-334 DC_GPIO_PAD_STRENGTH_2 DISPDEC:0x7ED8 2-334 DC_GPIO_PWRSEQ_A DISPDEC:0x7EA4 2-332 DC_GPIO_PWRSEQ_EN DISPDEC:0x7EA8 2-333 DC_GPIO_PWRSEQ_MASK DISPDEC:0x7EA0 2-332 DC_GPIO_PWRSEQ_Y DISPDEC:0x7EAC 2-333 DC_GPIO_SYNCA_A DISPDEC:0x7E74 2-330 DC_GPIO_SYNCA_EN DISPDEC:0x7E78 2-330 DC_GPIO_SYNCA_MASK DISPDEC:0x7E70 2-330 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-19...
  • Page 380 2-229 DC_LUTA_BLACK_OFFSET_GREEN DISPDEC:0x64C8 2-229 DC_LUTA_BLACK_OFFSET_RED DISPDEC:0x64CC 2-229 DC_LUTA_CONTROL DISPDEC:0x64C0 2-228 DC_LUTA_WHITE_OFFSET_BLUE DISPDEC:0x64D0 2-230 DC_LUTA_WHITE_OFFSET_GREEN DISPDEC:0x64D4 2-230 DC_LUTA_WHITE_OFFSET_RED DISPDEC:0x64D8 2-230 DC_LUTB_BLACK_OFFSET_BLUE DISPDEC:0x6CC4 2-260 DC_LUTB_BLACK_OFFSET_GREEN DISPDEC:0x6CC8 2-260 DC_LUTB_BLACK_OFFSET_RED DISPDEC:0x6CCC 2-260 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-20 Proprietary...
  • Page 381 2-319 DVOA_CRC_SIG_RESULT1 DISPDEC:0x79A4 2-319 DVOA_CRC_SIG_RESULT2 DISPDEC:0x79A8 2-319 DVOA_CRC2_SIG_MASK DISPDEC:0x79AC 2-319 DVOA_CRC2_SIG_RESULT DISPDEC:0x79B0 2-319 DVOA_ENABLE DISPDEC:0x7980 2-316 DVOA_FORCE_DATA DISPDEC:0x79BC 2-320 DVOA_FORCE_OUTPUT_CNTL DISPDEC:0x79B8 2-320 DVOA_OUTPUT DISPDEC:0x798C 2-317 DVOA_SOURCE_SELECT DISPDEC:0x7984 2-317 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-21...
  • Page 382 2-345 LVTMA_FORCE_DATA DISPDEC:0x7A90 2-341 LVTMA_FORCE_OUTPUT_CNTL DISPDEC:0x7A8C 2-341 LVTMA_LOAD_DETECT DISPDEC:0x7B08 2-352 LVTMA_LVDS_DATA_CNTL DISPDEC:0x7AFC 2-351 LVTMA_MACRO_CONTROL DISPDEC:0x7B0C 2-352 LVTMA_MODE DISPDEC:0x7B00 2-351 LVTMA_PWRSEQ_CNTL DISPDEC:0x7AF0 2-349 LVTMA_PWRSEQ_DELAY1 DISPDEC:0x7AE8 2-348 LVTMA_PWRSEQ_DELAY2 DISPDEC:0x7AEC 2-349 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-22 Proprietary...
  • Page 383 2-313 TMDSA_DATA_SYNCHRONIZATION DISPDEC:0x78D8 2-311 TMDSA_DCBALANCER_CONTROL DISPDEC:0x78D0 2-311 TMDSA_DEBUG DISPDEC:0x78C8 2-311 TMDSA_FORCE_DATA DISPDEC:0x7890 2-307 TMDSA_FORCE_OUTPUT_CNTL DISPDEC:0x788C 2-307 TMDSA_LOAD_DETECT DISPDEC:0x7908 2-315 TMDSA_MACRO_CONTROL DISPDEC:0x790C 2-315 TMDSA_RANDOM_PATTERN_SEED DISPDEC:0x78C4 2-310 TMDSA_RED_BLUE_SWITCH DISPDEC:0x78D4 2-311 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-23...
  • Page 384 2-197 VGA_MEM_WRITE_PAGE_ADDR DISPDEC:0x38 2-197 VGA_MEMORY_BASE_ADDRESS DISPDEC:0x310 2-188 VGA_MODE_CONTROL DISPDEC:0x308 2-187 VGA_RENDER_CONTROL DISPDEC:0x300 2-186 VGA_SEQUENCER_RESET_CONTROL DISPDEC:0x304 2-187 VGA_STATUS DISPDEC:0x340 2-190 VGA_STATUS_CLEAR DISPDEC:0x348 2-191 VGA_SURFACE_PITCH_SELECT DISPDEC:0x30C 2-187 VGA_TEST_CONTROL DISPDEC:0x354 2-193 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-24 Proprietary...

  • Page 385: Display Registers Stored By Address

    GENFC_WT 2-165 DISPDEC:0x3DA DISPDEC:0x3BA GENS1 2-167 DISPDEC:0x3DA VGA_MEM_READ_PAGE_ADDR DISPDEC:0x3C 2-197 ATTRDW DISPDEC:0x3C0 2-181 ATTRX DISPDEC:0x3C0 2-181 ATTRDR DISPDEC:0x3C1 2-181 GENMO_WT DISPDEC:0x3C2 2-165 GENMO_WT DISPDEC:0x3C2 2-194 GENS0 DISPDEC:0x3C2 2-166 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-25...
  • Page 386 2-272 D1CRTC_FORCE_COUNT_NOW_CNTL DISPDEC:0x6070 2-272 D1CRTC_FLOW_CONTROL DISPDEC:0x6074 2-272 D1CRTC_PIXEL_DATA_READBACK DISPDEC:0x6078 2-273 D1CRTC_STEREO_FORCE_NEXT_EYE DISPDEC:0x607C 2-273 D1CRTC_CONTROL DISPDEC:0x6080 2-273 D1CRTC_BLANK_CONTROL DISPDEC:0x6084 2-274 D1CRTC_INTERLACE_CONTROL DISPDEC:0x6088 2-274 D1CRTC_INTERLACE_STATUS DISPDEC:0x608C 2-274 D1CRTC_BLANK_DATA_COLOR DISPDEC:0x6090 2-275 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-26 Proprietary...
  • Page 387 2-200 D1GRPH_PITCH DISPDEC:0x6120 2-200 D1GRPH_SURFACE_OFFSET_X DISPDEC:0x6124 2-200 D1GRPH_SURFACE_OFFSET_Y DISPDEC:0x6128 2-200 D1GRPH_X_START DISPDEC:0x612C 2-200 D1GRPH_Y_START DISPDEC:0x6130 2-201 D1GRPH_X_END DISPDEC:0x6134 2-201 D1GRPH_Y_END DISPDEC:0x6138 2-201 D1COLOR_SPACE_CONVERT DISPDEC:0x613C 2-221 D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL DISPDEC:0x6140 2-217 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-27...
  • Page 388 2-209 D1OVL_PWL_40TO7F DISPDEC:0x6290 2-209 D1OVL_PWL_80TOBF DISPDEC:0x6294 2-210 D1OVL_PWL_C0TOFF DISPDEC:0x6298 2-210 D1OVL_PWL_100TO13F DISPDEC:0x629C 2-210 D1OVL_PWL_140TO17F DISPDEC:0x62A0 2-210 D1OVL_PWL_180TO1BF DISPDEC:0x62A4 2-210 D1OVL_PWL_1C0TO1FF DISPDEC:0x62A8 2-210 D1OVL_PWL_200TO23F DISPDEC:0x62AC 2-211 D1OVL_PWL_240TO27F DISPDEC:0x62B0 2-211 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-28 Proprietary...
  • Page 389 2-220 D1CUR_CONTROL DISPDEC:0x6400 2-222 D1CUR_SURFACE_ADDRESS DISPDEC:0x6408 2-222 D1CUR_SIZE DISPDEC:0x6410 2-222 D1CUR_POSITION DISPDEC:0x6414 2-222 D1CUR_HOT_SPOT DISPDEC:0x6418 2-223 D1CUR_COLOR1 DISPDEC:0x641C 2-223 D1CUR_COLOR2 DISPDEC:0x6420 2-223 D1CUR_UPDATE DISPDEC:0x6424 2-223 D1ICON_CONTROL DISPDEC:0x6440 2-224 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-29...
  • Page 390 2-282 D2CRTC_V_SYNC_A_CNTL DISPDEC:0x682C 2-283 D2CRTC_V_SYNC_B DISPDEC:0x6830 2-283 D2CRTC_V_SYNC_B_CNTL DISPDEC:0x6834 2-283 D2CRTC_TRIGA_CNTL DISPDEC:0x6860 2-283 D2CRTC_TRIGA_MANUAL_TRIG DISPDEC:0x6864 2-284 D2CRTC_TRIGB_CNTL DISPDEC:0x6868 2-285 D2CRTC_TRIGB_MANUAL_TRIG DISPDEC:0x686C 2-286 D2CRTC_FORCE_COUNT_NOW_CNTL DISPDEC:0x6870 2-286 D2CRTC_FLOW_CONTROL DISPDEC:0x6874 2-286 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-30 Proprietary...
  • Page 391 2-294 D2GRPH_ENABLE DISPDEC:0x6900 2-231 D2GRPH_CONTROL DISPDEC:0x6904 2-231 D2GRPH_LUT_SEL DISPDEC:0x6908 2-232 D2GRPH_PRIMARY_SURFACE_ADDRESS DISPDEC:0x6910 2-232 D2GRPH_SECONDARY_SURFACE_ADDRESS DISPDEC:0x6918 2-233 D2GRPH_PITCH DISPDEC:0x6920 2-233 D2GRPH_SURFACE_OFFSET_X DISPDEC:0x6924 2-233 D2GRPH_SURFACE_OFFSET_Y DISPDEC:0x6928 2-233 D2GRPH_X_START DISPDEC:0x692C 2-233 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-31...
  • Page 392 2-241 D2OVL_MATRIX_COEF_3_4 DISPDEC:0x6A30 2-241 D2OVL_PWL_TRANSFORM_EN DISPDEC:0x6A80 2-242 D2OVL_PWL_0TOF DISPDEC:0x6A84 2-242 D2OVL_PWL_10TO1F DISPDEC:0x6A88 2-242 D2OVL_PWL_20TO3F DISPDEC:0x6A8C 2-242 D2OVL_PWL_40TO7F DISPDEC:0x6A90 2-242 D2OVL_PWL_80TOBF DISPDEC:0x6A94 2-243 D2OVL_PWL_C0TOFF DISPDEC:0x6A98 2-243 D2OVL_PWL_100TO13F DISPDEC:0x6A9C 2-243 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-32 Proprietary...
  • Page 393 2-251 D2COLOR_MATRIX_COEF_2_4 DISPDEC:0x6BA0 2-252 D2COLOR_MATRIX_COEF_3_1 DISPDEC:0x6BA4 2-252 D2COLOR_MATRIX_COEF_3_2 DISPDEC:0x6BA8 2-252 D2COLOR_MATRIX_COEF_3_3 DISPDEC:0x6BAC 2-252 D2COLOR_MATRIX_COEF_3_4 DISPDEC:0x6BB0 2-253 D2CUR_CONTROL DISPDEC:0x6C00 2-255 D2CUR_SURFACE_ADDRESS DISPDEC:0x6C08 2-255 D2CUR_SIZE DISPDEC:0x6C10 2-255 D2CUR_POSITION DISPDEC:0x6C14 2-255 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-33...
  • Page 394 2-295 DACA_CRC_CONTROL DISPDEC:0x780C 2-295 DACA_CRC_SIG_RGB_MASK DISPDEC:0x7810 2-295 DACA_CRC_SIG_CONTROL_MASK DISPDEC:0x7814 2-296 DACA_CRC_SIG_RGB DISPDEC:0x7818 2-296 DACA_CRC_SIG_CONTROL DISPDEC:0x781C 2-296 DACA_SYNC_TRISTATE_CONTROL DISPDEC:0x7820 2-296 DACA_SYNC_SELECT DISPDEC:0x7824 2-296 DACA_AUTODETECT_CONTROL DISPDEC:0x7828 2-297 DACA_AUTODETECT_CONTROL2 DISPDEC:0x782C 2-297 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-34 Proprietary...
  • Page 395 2-311 TMDSA_DCBALANCER_CONTROL DISPDEC:0x78D0 2-311 TMDSA_RED_BLUE_SWITCH DISPDEC:0x78D4 2-311 TMDSA_DATA_SYNCHRONIZATION DISPDEC:0x78D8 2-311 TMDSA_CTL0_1_GEN_CNTL DISPDEC:0x78DC 2-312 TMDSA_CTL2_3_GEN_CNTL DISPDEC:0x78E0 2-313 TMDSA_TRANSMITTER_ENABLE DISPDEC:0x7904 2-314 TMDSA_LOAD_DETECT DISPDEC:0x7908 2-315 TMDSA_MACRO_CONTROL DISPDEC:0x790C 2-315 TMDSA_TRANSMITTER_CONTROL DISPDEC:0x7910 2-315 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-35...
  • Page 396 2-303 DACB_AUTODETECT_INT_CONTROL DISPDEC:0x7A38 2-303 DACB_FORCE_OUTPUT_CNTL DISPDEC:0x7A3C 2-303 DACB_FORCE_DATA DISPDEC:0x7A40 2-304 DACB_POWERDOWN DISPDEC:0x7A50 2-304 DACB_CONTROL1 DISPDEC:0x7A54 2-304 DACB_CONTROL2 DISPDEC:0x7A58 2-304 DACB_COMPARATOR_ENABLE DISPDEC:0x7A5C 2-305 DACB_COMPARATOR_OUTPUT DISPDEC:0x7A60 2-305 DACB_TEST_ENABLE DISPDEC:0x7A64 2-305 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-36 Proprietary...
  • Page 397 2-350 LVTMA_BL_MOD_CNTL DISPDEC:0x7AF8 2-350 LVTMA_LVDS_DATA_CNTL DISPDEC:0x7AFC 2-351 LVTMA_MODE DISPDEC:0x7B00 2-351 LVTMA_TRANSMITTER_ENABLE DISPDEC:0x7B04 2-351 LVTMA_LOAD_DETECT DISPDEC:0x7B08 2-352 LVTMA_MACRO_CONTROL DISPDEC:0x7B0C 2-352 LVTMA_TRANSMITTER_CONTROL DISPDEC:0x7B10 2-353 LVTMA_REG_TEST_OUTPUT DISPDEC:0x7B14 2-354 LVTMA_TRANSMITTER_DEBUG DISPDEC:0x7B18 2-354 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-37...
  • Page 398 2-328 DC_GPIO_DDC1_Y DISPDEC:0x7E4C 2-328 DC_GPIO_DDC2_MASK DISPDEC:0x7E50 2-328 DC_GPIO_DDC2_A DISPDEC:0x7E54 2-329 DC_GPIO_DDC2_EN DISPDEC:0x7E58 2-329 DC_GPIO_DDC2_Y DISPDEC:0x7E5C 2-329 DC_GPIO_DDC3_MASK DISPDEC:0x7E60 2-329 DC_GPIO_DDC3_A DISPDEC:0x7E64 2-329 DC_GPIO_DDC3_EN DISPDEC:0x7E68 2-330 DC_GPIO_DDC3_Y DISPDEC:0x7E6C 2-330 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-38 Proprietary...
  • Page 399 2-336 DISP_TIMER_CONTROL DISPDEC:0x7EF0 2-337 DO_PERFCOUNTER0_SELECT DISPDEC:0x7F00 2-338 DO_PERFCOUNTER0_HI DISPDEC:0x7F04 2-338 DO_PERFCOUNTER0_LOW DISPDEC:0x7F08 2-338 DO_PERFCOUNTER1_SELECT DISPDEC:0x7F0C 2-338 DO_PERFCOUNTER1_HI DISPDEC:0x7F10 2-338 DO_PERFCOUNTER1_LOW DISPDEC:0x7F14 2-338 DCO_PERFMON_CNTL_R DISPDEC:0x7F18 2-339 CRTC_EXT_CNTL DISPDEC:0xE054 2-196 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-39...

  • Page 400: Host Interface Decode Space Registers Sorted By Name

    2-58 GENMO_RD HIDEC:0x3CC 2-106 GENMO_WT HIDEC:0x3C2 2-106 MM_DATA HIDEC:0x4 2-58 MM_INDEX HIDEC:0x0 2-58 MSI_REARM_EN HIDEC:0x160 2-60 PCIE_DATA HIDEC:0x38 2-106 PCIE_DATA HIDEC:0x38 2-115 PCIE_INDEX HIDEC:0x30 2-106 PCIE_INDEX HIDEC:0x30 2-114 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-40 Proprietary...

  • Page 401: Memory Controller Registers Sorted By Name

    2-22 MC_IO_RD_QS_CNTL_I1 MCIND:0x87 2-22 MC_IO_RD_QS2_CNTL_I0 MCIND:0x9C 2-28 MC_IO_RD_QS2_CNTL_I1 MCIND:0x9D 2-28 MC_IO_WR_CNTL_I0 MCIND:0x88 2-22 MC_IO_WR_CNTL_I1 MCIND:0x89 2-23 MC_IO_WR_DQ_CNTL_I0 MCIND:0x94 2-26 MC_IO_WR_DQ_CNTL_I1 MCIND:0x95 2-26 MC_IO_WR_QS_CNTL_I0 MCIND:0x96 2-26 MC_IO_WR_QS_CNTL_I1 MCIND:0x97 2-27 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-41...
  • Page 402 2-33 MC_PT0_CONTEXT2_DEFAULT_READ_ADDR MCIND:0x11E 2-37 MC_PT0_CONTEXT2_FLAT_BASE_ADDR MCIND:0x12E 2-38 MC_PT0_CONTEXT2_FLAT_END_ADDR MCIND:0x14E 2-40 MC_PT0_CONTEXT2_FLAT_START_ADDR MCIND:0x13E 2-39 MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR MCIND:0x15E 2-42 MC_PT0_CONTEXT3_CNTL MCIND:0x105 2-34 MC_PT0_CONTEXT3_DEFAULT_READ_ADDR MCIND:0x11F 2-37 MC_PT0_CONTEXT3_FLAT_BASE_ADDR MCIND:0x12F 2-38 MC_PT0_CONTEXT3_FLAT_END_ADDR MCIND:0x14F 2-41 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-42 Proprietary...
  • Page 403 2-18 MC_SEQ_A_PAD_CNTL_I1 MCIND:0x75 2-18 MC_SEQ_CAS_TIMING MCIND:0x62 2-11 MC_SEQ_CK_PAD_CNTL_I0 MCIND:0x6C 2-16 MC_SEQ_CK_PAD_CNTL_I1 MCIND:0x6D 2-16 MC_SEQ_CMD MCIND:0x76 2-19 MC_SEQ_CMD_PAD_CNTL_I0 MCIND:0x6E 2-17 MC_SEQ_CMD_PAD_CNTL_I1 MCIND:0x6F 2-17 MC_SEQ_DQ_PAD_CNTL_I0 MCIND:0x70 2-17 MC_SEQ_DQ_PAD_CNTL_I1 MCIND:0x71 2-17 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-43...
  • Page 404 MCIND:0x65 2-13 MC_SEQ_STATUS MCIND:0x77 2-19 MC_SEQ_WR_CTL_I0 MCIND:0x66 2-14 MC_SEQ_WR_CTL_I1 MCIND:0x67 2-15 MC_STATUS MCIND:0x0 MC_SW_CNTL MCIND:0x18 MC_TIMING_CNTL_2 MCIND:0x3 MC_VENDOR_ID_I0 MCIND:0x98 2-27 MC_VENDOR_ID_I1 MCIND:0x99 2-27 MC_WRITE_AGE1 MCIND:0x37 MC_WRITE_AGE2 MCIND:0x38 2-10 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-44 Proprietary...

  • Page 405: Memory Controller Registers Sorted By Address

    MCIND:0x131 2-38 MC_PT0_CONTEXT6_FLAT_BASE_ADDR MCIND:0x132 2-38 MC_PT0_CONTEXT7_FLAT_BASE_ADDR MCIND:0x133 2-39 MC_PT0_CONTEXT0_FLAT_START_ADDR MCIND:0x13C 2-39 MC_PT0_CONTEXT1_FLAT_START_ADDR MCIND:0x13D 2-39 MC_PT0_CONTEXT2_FLAT_START_ADDR MCIND:0x13E 2-39 MC_PT0_CONTEXT3_FLAT_START_ADDR MCIND:0x13F 2-39 MC_ARB_DRAM_PENALTIES2 MCIND:0x14 MC_PT0_CONTEXT4_FLAT_START_ADDR MCIND:0x140 2-39 MC_PT0_CONTEXT5_FLAT_START_ADDR MCIND:0x141 2-40 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-45...
  • Page 406 2-54 MC_PT0_CLIENT14_CNTL MCIND:0x17A 2-55 MC_PT0_CLIENT15_CNTL MCIND:0x17B 2-55 MC_PT0_CLIENT16_CNTL MCIND:0x17C 2-56 MC_SW_CNTL MCIND:0x18 MC_TIMING_CNTL_2 MCIND:0x3 MC_WRITE_AGE1 MCIND:0x37 MC_WRITE_AGE2 MCIND:0x38 2-10 MC_FB_LOCATION MCIND:0x4 MC_AGP_LOCATION MCIND:0x5 AGP_BASE MCIND:0x6 MC_SEQ_DRAM MCIND:0x60 2-10 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-46 Proprietary...
  • Page 407 MCIND:0x8C 2-23 MC_IO_CMD_PAD_CNTL_I1 MCIND:0x8D 2-24 MC_IO_DQ_PAD_CNTL_I0 MCIND:0x8E 2-24 MC_IO_DQ_PAD_CNTL_I1 MCIND:0x8F 2-24 MC_CNTL1 MCIND:0x9 MC_IO_QS_PAD_CNTL_I0 MCIND:0x90 2-25 MC_IO_QS_PAD_CNTL_I1 MCIND:0x91 2-25 MC_IO_A_PAD_CNTL_I0 MCIND:0x92 2-25 MC_IO_A_PAD_CNTL_I1 MCIND:0x93 2-26 MC_IO_WR_DQ_CNTL_I0 MCIND:0x94 2-26 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-47...
  • Page 408 2-28 MC_RBS_MAP MCIND:0xB0 2-29 MC_RBS_CZT_HWM MCIND:0xB1 2-30 MC_RBS_SUN_HWM MCIND:0xB2 2-30 MC_RBS_MISC MCIND:0xB3 2-30 MC_PMG_CMD MCIND:0xE0 2-31 MC_PMG_CFG MCIND:0xE1 2-31 MC_MISC_0 MCIND:0xF0 2-31 MC_MISC_1 MCIND:0xF1 2-31 MC_DEBUG MCIND:0xFE 2-32 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-48 Proprietary...

  • Page 409: Pcie Registers Sorted By Name

    2-104 PCIE_P_DECODE_ERR_CNT_8 PCIEIND:0xF8 2-104 PCIE_P_DECODE_ERR_CNT_9 PCIEIND:0xF9 2-104 PCIE_P_DECODE_ERR_CNTL PCIEIND:0xC5 2-103 PCIE_P_DECODER_STATUS PCIEIND:0xB3 2-99 PCIE_P_IMP_CNTL_STRENGTH PCIEIND:0xC0 2-101 PCIE_P_IMP_CNTL_UPDATE PCIEIND:0xC1 2-102 PCIE_P_MISC_DEBUG_STATUS PCIEIND:0xB4 2-100 PCIE_P_PAD_MISC_CNTL PCIEIND:0xC3 2-102 PCIE_P_STR_CNTL_UPDATE PCIEIND:0xC2 2-102 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-49...
  • Page 410 2-111 PCIE_RESERVED PCIEIND:0x0 2-80 PCIE_RX_ACK_NACK_LATENCY PCIEIND:0x73 2-91 PCIE_RX_ACK_NACK_LATENCY_THRESHOLD PCIEIND:0x74 2-91 PCIE_RX_CNTL PCIEIND:0x70 2-90 PCIE_RX_CREDITS_ALLOCATED PCIEIND:0x7E 2-92 PCIE_RX_CREDITS_ALLOCATED_CPLD PCIEIND:0x80 2-93 PCIE_RX_CREDITS_ALLOCATED_D PCIEIND:0x7F 2-93 PCIE_RX_CREDITS_RECEIVED PCIEIND:0x81 2-93 PCIE_RX_CREDITS_RECEIVED_CPLD PCIEIND:0x83 2-93 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-50 Proprietary...
  • Page 411 2-86 PCIE_TX_GART_TLB11_DATA PCIEIND:0x2E 2-86 PCIE_TX_GART_TLB12_DATA PCIEIND:0x2F 2-86 PCIE_TX_GART_TLB13_DATA PCIEIND:0x30 2-86 PCIE_TX_GART_TLB14_DATA PCIEIND:0x31 2-86 PCIE_TX_GART_TLB15_DATA PCIEIND:0x32 2-86 PCIE_TX_GART_TLB16_DATA PCIEIND:0x33 2-87 PCIE_TX_GART_TLB17_DATA PCIEIND:0x34 2-87 PCIE_TX_GART_TLB18_DATA PCIEIND:0x35 2-87 PCIE_TX_GART_TLB19_DATA PCIEIND:0x36 2-87 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-51...
  • Page 412 2-85 PCIE_TX_GART_TLB8_DATA PCIEIND:0x2B 2-85 PCIE_TX_GART_TLB9_DATA PCIEIND:0x2C 2-85 PCIE_TX_REPLAY PCIEIND:0x3 2-80 PCIE_TX_SEQ PCIEIND:0x2 2-80 PCIE_TXRX_DEBUG_SEQNUM PCIEIND:0x61 2-90 PCIE_TXRX_TEST_MODE PCIEIND:0x62 2-90 PCIE_XSTRAP1 PCIEIND:0x425 2-113 PCIE_XSTRAP2 PCIEIND:0x426 2-114 PCIE_XSTRAP5 PCIEIND:0x429 2-114 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-52 Proprietary...

  • Page 413: Pcie Registers Sorted By Address

    2-87 PCIE_TX_GART_TLB18_DATA PCIEIND:0x35 2-87 PCIE_TX_GART_TLB19_DATA PCIEIND:0x36 2-87 PCIE_TX_GART_TLB20_DATA PCIEIND:0x37 2-87 PCIE_TX_GART_TLB21_DATA PCIEIND:0x38 2-87 PCIE_TX_GART_TLB22_DATA PCIEIND:0x39 2-88 PCIE_TX_GART_TLB23_DATA PCIEIND:0x3A 2-88 PCIE_TX_GART_TLB24_DATA PCIEIND:0x3B 2-88 PCIE_TX_GART_TLB25_DATA PCIEIND:0x3C 2-88 PCIE_TX_GART_TLB26_DATA PCIEIND:0x3D 2-88 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-53...
  • Page 414 2-111 PCIE_TX_GART_TLB31_DATA PCIEIND:0x42 2-89 PCIE_PRBS23_ERRCNT14 PCIEIND:0x420 2-112 PCIE_PRBS23_ERRCNT15 PCIEIND:0x421 2-112 PCIE_PRBS23_CTRL0 PCIEIND:0x422 2-112 PCIE_PRBS23_CTRL1 PCIEIND:0x423 2-113 PCIE_PRBS_EN PCIEIND:0x424 2-113 PCIE_XSTRAP1 PCIEIND:0x425 2-113 PCIE_XSTRAP2 PCIEIND:0x426 2-114 PCIE_XSTRAP5 PCIEIND:0x429 2-114 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-54 Proprietary...
  • Page 415 2-95 PCIE_LC_LINK_WIDTH_CNTL PCIEIND:0xA2 2-97 PCIE_LC_STATE0 PCIEIND:0xA5 2-95 PCIE_LC_STATE1 PCIEIND:0xA6 2-96 PCIE_LC_STATE2 PCIEIND:0xA7 2-96 PCIE_LC_STATE3 PCIEIND:0xA8 2-96 PCIE_LC_STATE4 PCIEIND:0xA9 2-96 PCIE_LC_STATE5 PCIEIND:0xAA 2-96 PCIE_LC_FORCE_SYNC_LOSS_CNTL PCIEIND:0xAB 2-97 PCIE_P_CNTL PCIEIND:0xB0 2-97 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-55...
  • Page 416 2-104 PCIE_P_DECODE_ERR_CNT_7 PCIEIND:0xF7 2-104 PCIE_P_DECODE_ERR_CNT_8 PCIEIND:0xF8 2-104 PCIE_P_DECODE_ERR_CNT_9 PCIEIND:0xF9 2-104 PCIE_P_DECODE_ERR_CNT_10 PCIEIND:0xFA 2-104 PCIE_P_DECODE_ERR_CNT_11 PCIEIND:0xFB 2-104 PCIE_P_DECODE_ERR_CNT_12 PCIEIND:0xFC 2-105 PCIE_P_DECODE_ERR_CNT_13 PCIEIND:0xFD 2-105 PCIE_P_DECODE_ERR_CNT_14 PCIEIND:0xFE 2-105 PCIE_P_DECODE_ERR_CNT_15 PCIEIND:0xFF 2-105 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-56 Proprietary...

  • Page 417: Vip Registers Sorted By Name

    2-141 DMA_VIPH_ABORT VIPDEC:0xA88 2-142 DMA_VIPH_CHUNK_0 VIPDEC:0xA18 2-139 DMA_VIPH_CHUNK_1_VAL VIPDEC:0xA1C 2-140 DMA_VIPH_MISC_CNTL VIPDEC:0xA14 2-149 DMA_VIPH_STATUS VIPDEC:0xA10 2-139 DMA_VIPH0_ACTIVE VIPDEC:0xA24 2-141 DMA_VIPH0_COMMAND VIPDEC:0xA00 2-137 DMA_VIPH0_COMMAND VIPDEC:0xA00 2-144 DMA_VIPH1_ACTIVE VIPDEC:0xA34 2-141 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-57...
  • Page 418 2-122 VIPH_CH0_ADDR VIPDEC:0xC10 2-120 VIPH_CH0_DATA VIPDEC:0xC00 2-120 VIPH_CH0_SBCNT VIPDEC:0xC20 2-121 VIPH_CH1_ABCNT VIPDEC:0xC34 2-122 VIPH_CH1_ADDR VIPDEC:0xC14 2-121 VIPH_CH1_DATA VIPDEC:0xC04 2-120 VIPH_CH1_SBCNT VIPDEC:0xC24 2-121 VIPH_CH2_ABCNT VIPDEC:0xC38 2-122 VIPH_CH2_ADDR VIPDEC:0xC18 2-121 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-58 Proprietary...
  • Page 419 2-123 VIPH_REG_ADDR VIPDEC:0x80 2-125 VIPH_REG_DATA VIPDEC:0x84 2-125 VIPH_TIMEOUT_STAT VIPDEC:0xC50 2-124 VIPPAD_A VIPDEC:0xC58 2-150 VIPPAD_EN VIPDEC:0xC5C 2-151 VIPPAD_MASK VIPDEC:0xC54 2-150 VIPPAD_STRENGTH VIPDEC:0x1B8 2-148 VIPPAD_Y VIPDEC:0xC60 2-151 ZV_LCDPAD_Y VIPDEC:0x1B4 2-148 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-59...

  • Page 420: Vip Registers Sorted By Address

    2-127 CAP0_BUF1_EVEN_OFFSET VIPDEC:0x92C 2-127 CAP0_BUF_PITCH VIPDEC:0x930 2-127 CAP0_V_WINDOW VIPDEC:0x934 2-128 CAP0_H_WINDOW VIPDEC:0x938 2-128 CAP0_VBI0_OFFSET VIPDEC:0x93C 2-128 I2C_CNTL_1 VIPDEC:0x94 2-118 CAP0_VBI1_OFFSET VIPDEC:0x940 2-128 CAP0_VBI_V_WINDOW VIPDEC:0x944 2-128 CAP0_VBI_H_WINDOW VIPDEC:0x948 2-128 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-60 Proprietary...
  • Page 421 2-148 VIPH_CH0_DATA VIPDEC:0xC00 2-120 VIPH_CH1_DATA VIPDEC:0xC04 2-120 VIPH_CH2_DATA VIPDEC:0xC08 2-120 VIPH_CH3_DATA VIPDEC:0xC0C 2-120 VIPH_CH0_ADDR VIPDEC:0xC10 2-120 VIPH_CH1_ADDR VIPDEC:0xC14 2-121 VIPH_CH2_ADDR VIPDEC:0xC18 2-121 VIPH_CH3_ADDR VIPDEC:0xC1C 2-121 VIPH_CH0_SBCNT VIPDEC:0xC20 2-121 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-61...
  • Page 422 2-123 VIPH_DV_INT VIPDEC:0xC4C 2-124 VIPH_TIMEOUT_STAT VIPDEC:0xC50 2-124 VIPPAD_MASK VIPDEC:0xC54 2-150 VIPPAD_A VIPDEC:0xC58 2-150 VIPPAD_EN VIPDEC:0xC5C 2-151 VIPPAD_Y VIPDEC:0xC60 2-151 MAXX_PWM VIPDEC:0xC64 2-152 CONFIG_XSTRAP VIPDEC:0xE4 2-144 CONFIG_GPIO VIPDEC:0xE8 2-145 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-62 Proprietary...

  • Page 423: Vga Attr Registers Sorted By Name

    2-183 ATTR0C VGAATTRIND:0xC 2-183 ATTR0D VGAATTRIND:0xD 2-183 ATTR0E VGAATTRIND:0xE 2-184 ATTR0F VGAATTRIND:0xF 2-184 ATTR10 VGAATTRIND:0x10 2-184 ATTR11 VGAATTRIND:0x11 2-184 ATTR12 VGAATTRIND:0x12 2-185 ATTR13 VGAATTRIND:0x13 2-185 ATTR14 VGAATTRIND:0x14 2-185 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-63...

  • Page 424: Vga Crt Registers Sorted By Name

    2-175 CRT13 VGACRTIND:0x13 2-176 CRT14 VGACRTIND:0x14 2-176 CRT15 VGACRTIND:0x15 2-176 CRT16 VGACRTIND:0x16 2-176 CRT17 VGACRTIND:0x17 2-176 CRT18 VGACRTIND:0x18 2-177 CRT1E VGACRTIND:0x1E 2-177 CRT1F VGACRTIND:0x1F 2-177 CRT22 VGACRTIND:0x22 2-177 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-64 Proprietary...

  • Page 425: Vga Grph Registers Sorted By Name

    Page GRA00 VGAGRPHIND:0x0 2-178 GRA01 VGAGRPHIND:0x1 2-178 GRA02 VGAGRPHIND:0x2 2-178 GRA03 VGAGRPHIND:0x3 2-179 GRA04 VGAGRPHIND:0x4 2-179 GRA05 VGAGRPHIND:0x5 2-179 GRA06 VGAGRPHIND:0x6 2-180 GRA07 VGAGRPHIND:0x7 2-180 GRA08 VGAGRPHIND:0x8 2-180 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-65...

  • Page 426: Vga Seq Registers Sorted By Name

    VGA SEQ Registers Sorted By Name Table A-17 VGA SEQ Registers Sorted by Name Register Name Address Page SEQ00 VGASEQIND:0x0 2-169 SEQ01 VGASEQIND:0x1 2-169 SEQ02 VGASEQIND:0x2 2-169 SEQ03 VGASEQIND:0x3 2-170 SEQ04 VGASEQIND:0x4 2-170 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-66 Proprietary...

  • Page 427: All Registers Sorted By Name

    ATTR14 2-185 ATTRDR 2-181 ATTRDW 2-181 ATTRX 2-181 BASE_CODE 2-62 BIOS_ROM 2-64 BIST 2-63 BUS_CNTL 2-58 CACHE_LINE 2-62 CAP_INT_CNTL 2-133 CAP_INT_STATUS 2-134 CAP0_ANC_BUF01_BLOCK_CNT 2-149 CAP0_ANC_BUF23_BLOCK_CNT 2-149 CAP0_ANC_H_WINDOW 2-131 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-67...
  • Page 428 CG_CLKPIN_CNTL 2-163 CG_MISC_REG 2-161 CG_TC_JTAG_0 2-164 CG_TC_JTAG_1 2-164 CLOCK_CNTL_DATA 2-155 CLOCK_CNTL_INDEX 2-155 COMMAND 2-61 CONFIG_APER_0_BASE 2-59 CONFIG_APER_1_BASE 2-60 CONFIG_APER_SIZE 2-60 CONFIG_CNTL 2-59 CONFIG_GPIO 2-145 CONFIG_MEMSIZE 2-59 CONFIG_REG_1_BASE 2-60 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-68 Proprietary...
  • Page 429 CRT18 2-177 CRT1E 2-177 CRT1F 2-177 CRT22 2-177 CRTC_EXT_CNTL 2-196 CRTC8_DATA 2-171 CRTC8_DATA 2-196 CRTC8_IDX 2-171 CRTC8_IDX 2-196 D1COLOR_MATRIX_COEF_1_1 2-217 D1COLOR_MATRIX_COEF_1_2 2-217 D1COLOR_MATRIX_COEF_1_3 2-218 D1COLOR_MATRIX_COEF_1_4 2-218 D1COLOR_MATRIX_COEF_2_1 2-218 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-69...
  • Page 430 D1CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 2-276 D1CRTC_OVERSCAN_COLOR 2-275 D1CRTC_PIXEL_DATA_READBACK 2-273 D1CRTC_SNAPSHOT_CONTROL 2-278 D1CRTC_SNAPSHOT_FRAME 2-278 D1CRTC_SNAPSHOT_POSITION 2-278 D1CRTC_SNAPSHOT_STATUS 2-278 D1CRTC_START_LINE_CONTROL 2-278 D1CRTC_STATUS 2-275 D1CRTC_STATUS_FRAME_COUNT 2-276 D1CRTC_STATUS_HV_COUNT 2-276 D1CRTC_STATUS_POSITION 2-276 D1CRTC_STATUS_VF_COUNT 2-276 D1CRTC_STEREO_CONTROL 2-277 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-70 Proprietary...
  • Page 431 D1GRPH_ENABLE 2-198 D1GRPH_FLIP_CONTROL 2-202 D1GRPH_KEY_RANGE_ALPHA 2-215 D1GRPH_KEY_RANGE_BLUE 2-215 D1GRPH_KEY_RANGE_GREEN 2-214 D1GRPH_KEY_RANGE_RED 2-214 D1GRPH_LUT_SEL 2-199 D1GRPH_PITCH 2-200 D1GRPH_PRIMARY_SURFACE_ADDRESS 2-199 D1GRPH_SECONDARY_SURFACE_ADDRESS 2-200 D1GRPH_SURFACE_ADDRESS_INUSE 2-202 D1GRPH_SURFACE_OFFSET_X 2-200 D1GRPH_SURFACE_OFFSET_Y 2-200 D1GRPH_UPDATE 2-201 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-71...
  • Page 432 D1OVL_MATRIX_COEF_1_2 2-206 D1OVL_MATRIX_COEF_1_3 2-206 D1OVL_MATRIX_COEF_1_4 2-206 D1OVL_MATRIX_COEF_2_1 2-207 D1OVL_MATRIX_COEF_2_2 2-207 D1OVL_MATRIX_COEF_2_3 2-207 D1OVL_MATRIX_COEF_2_4 2-207 D1OVL_MATRIX_COEF_3_1 2-207 D1OVL_MATRIX_COEF_3_2 2-208 D1OVL_MATRIX_COEF_3_3 2-208 D1OVL_MATRIX_COEF_3_4 2-208 D1OVL_MATRIX_TRANSFORM_EN 2-206 D1OVL_PITCH 2-204 D1OVL_PWL_0TOF 2-209 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-72 Proprietary...
  • Page 433 D2COLOR_MATRIX_COEF_1_2 2-250 D2COLOR_MATRIX_COEF_1_3 2-250 D2COLOR_MATRIX_COEF_1_4 2-251 D2COLOR_MATRIX_COEF_2_1 2-251 D2COLOR_MATRIX_COEF_2_2 2-251 D2COLOR_MATRIX_COEF_2_3 2-251 D2COLOR_MATRIX_COEF_2_4 2-252 D2COLOR_MATRIX_COEF_3_1 2-252 D2COLOR_MATRIX_COEF_3_2 2-252 D2COLOR_MATRIX_COEF_3_3 2-252 D2COLOR_MATRIX_COEF_3_4 2-253 D2COLOR_SPACE_CONVERT 2-254 D2CRTC_BLACK_COLOR 2-289 D2CRTC_BLANK_CONTROL 2-287 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-73...
  • Page 434 D2CRTC_STATUS_HV_COUNT 2-290 D2CRTC_STATUS_POSITION 2-289 D2CRTC_STATUS_VF_COUNT 2-290 D2CRTC_STEREO_CONTROL 2-291 D2CRTC_STEREO_FORCE_NEXT_EYE 2-287 D2CRTC_STEREO_STATUS 2-291 D2CRTC_TRIGA_CNTL 2-283 D2CRTC_TRIGA_MANUAL_TRIG 2-284 D2CRTC_TRIGB_CNTL 2-285 D2CRTC_TRIGB_MANUAL_TRIG 2-286 D2CRTC_UPDATE_LOCK 2-293 D2CRTC_V_BLANK_START_END 2-282 D2CRTC_V_SYNC_A 2-282 D2CRTC_V_SYNC_A_CNTL 2-283 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-74 Proprietary...
  • Page 435 D2GRPH_SURFACE_ADDRESS_INUSE 2-235 D2GRPH_SURFACE_OFFSET_X 2-233 D2GRPH_SURFACE_OFFSET_Y 2-233 D2GRPH_UPDATE 2-234 D2GRPH_X_END 2-234 D2GRPH_X_START 2-233 D2GRPH_Y_END 2-234 D2GRPH_Y_START 2-234 D2ICON_COLOR1 2-257 D2ICON_COLOR2 2-258 D2ICON_CONTROL 2-257 D2ICON_SIZE 2-257 D2ICON_START_POSITION 2-257 D2ICON_SURFACE_ADDRESS 2-257 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-75...
  • Page 436 D2OVL_MATRIX_COEF_3_4 2-241 D2OVL_MATRIX_TRANSFORM_EN 2-239 D2OVL_PITCH 2-237 D2OVL_PWL_0TOF 2-242 D2OVL_PWL_100TO13F 2-243 D2OVL_PWL_10TO1F 2-242 D2OVL_PWL_140TO17F 2-243 D2OVL_PWL_180TO1BF 2-243 D2OVL_PWL_1C0TO1FF 2-243 D2OVL_PWL_200TO23F 2-244 D2OVL_PWL_20TO3F 2-242 D2OVL_PWL_240TO27F 2-244 D2OVL_PWL_280TO2BF 2-244 D2OVL_PWL_2C0TO2FF 2-244 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-76 Proprietary...
  • Page 437 DACA_CONTROL2 2-299 DACA_CRC_CONTROL 2-295 DACA_CRC_EN 2-295 DACA_CRC_SIG_CONTROL 2-296 DACA_CRC_SIG_CONTROL_MASK 2-296 DACA_CRC_SIG_RGB 2-296 DACA_CRC_SIG_RGB_MASK 2-295 DACA_ENABLE 2-295 DACA_FORCE_DATA 2-298 DACA_FORCE_OUTPUT_CNTL 2-298 DACA_POWERDOWN 2-298 DACA_PWR_CNTL 2-300 DACA_SOURCE_SELECT 2-295 DACA_SYNC_SELECT 2-296 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-77...
  • Page 438 DC_CRTC_TV_CONTROL 2-280 DC_GENERICA 2-324 DC_GENERICB 2-325 DC_GPIO_DDC1_A 2-328 DC_GPIO_DDC1_EN 2-328 DC_GPIO_DDC1_MASK 2-328 DC_GPIO_DDC1_Y 2-328 DC_GPIO_DDC2_A 2-329 DC_GPIO_DDC2_EN 2-329 DC_GPIO_DDC2_MASK 2-328 DC_GPIO_DDC2_Y 2-329 DC_GPIO_DDC3_A 2-329 DC_GPIO_DDC3_EN 2-330 DC_GPIO_DDC3_MASK 2-329 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-78 Proprietary...
  • Page 439 DC_GPIO_SYNCB_Y 2-331 DC_GPIO_VIP_DEBUG 2-326 DC_HOT_PLUG_DETECT_CLOCK_CONTROL 2-322 DC_HOT_PLUG_DETECT1_CONTROL 2-320 DC_HOT_PLUG_DETECT1_INT_CONTROL 2-321 DC_HOT_PLUG_DETECT1_INT_STATUS 2-321 DC_HOT_PLUG_DETECT2_CONTROL 2-321 DC_HOT_PLUG_DETECT2_INT_CONTROL 2-321 DC_HOT_PLUG_DETECT2_INT_STATUS 2-321 DC_I2C_ARBITRATION 2-324 DC_I2C_CONTROL1 2-322 DC_I2C_CONTROL2 2-323 DC_I2C_CONTROL3 2-323 DC_I2C_DATA 2-323 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-79...
  • Page 440 DC_PAD_EXTERN_SIG 2-325 DC_REF_CLK_CNTL 2-325 DCO_PERFMON_CNTL_R 2-339 DCP_CRC_CONTROL 2-262 DCP_CRC_MASK 2-262 DCP_CRC_P0_CURRENT 2-262 DCP_CRC_P0_LAST 2-262 DCP_CRC_P1_CURRENT 2-262 DCP_CRC_P1_LAST 2-263 DCP_LB_DATA_GAP_BETWEEN_CHUNK 2-266 DEVICE_CAP 2-67 DEVICE_CNTL 2-67 DEVICE_ID 2-61 DEVICE_STATUS 2-68 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-80 Proprietary...
  • Page 441 DO_PERFCOUNTER1_HI 2-338 DO_PERFCOUNTER1_LOW 2-338 DO_PERFCOUNTER1_SELECT 2-338 DOUT_POWER_MANAGEMENT_CNTL 2-336 DVOA_BIT_DEPTH_CONTROL 2-317 DVOA_CONTROL 2-318 DVOA_CRC_CONTROL 2-318 DVOA_CRC_EN 2-318 DVOA_CRC_SIG_MASK1 2-319 DVOA_CRC_SIG_MASK2 2-319 DVOA_CRC_SIG_RESULT1 2-319 DVOA_CRC_SIG_RESULT2 2-319 DVOA_CRC2_SIG_MASK 2-319 DVOA_CRC2_SIG_RESULT 2-319 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-81...
  • Page 442 F1_LATENCY 2-74 F1_LINK_CAP 2-79 F1_LINK_CNTL 2-79 F1_LINK_STATUS 2-79 F1_MAX_LATENCY 2-76 F1_MIN_GRANT 2-76 F1_PCIE_CAP 2-77 F1_PCIE_CAP_LIST 2-77 F1_PMI_BSE 2-77 F1_PMI_CAP_ID 2-76 F1_PMI_DATA 2-77 F1_PMI_NXT_CAP_PTR 2-76 F1_PMI_PMC_REG 2-76 F1_PMI_STATUS 2-77 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-82 Proprietary...
  • Page 443 GENMO_RD 2-106 GENMO_WT 2-165 GENMO_WT 2-194 GENMO_WT 2-106 GENS0 2-166 GENS1 2-167 GPIO_STRENGTH 2-147 GPIOPAD_A 2-147 GPIOPAD_EN 2-147 GPIOPAD_MASK 2-147 GPIOPAD_Y 2-147 GRA00 2-178 GRA01 2-178 GRA02 2-178 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-83...
  • Page 444 LVTMA_COLOR_FORMAT 2-341 LVTMA_CONTROL_CHAR 2-342 LVTMA_CONTROL0_FEEDBACK 2-342 LVTMA_CRC_CNTL 2-343 LVTMA_CRC_SIG_MASK 2-343 LVTMA_CRC_SIG_RGB 2-344 LVTMA_CTL_BITS 2-345 LVTMA_CTL0_1_GEN_CNTL 2-346 LVTMA_CTL2_3_GEN_CNTL 2-347 LVTMA_DATA_SYNCHRONIZATION 2-346 LVTMA_DCBALANCER_CONTROL 2-345 LVTMA_DEBUG 2-345 LVTMA_FORCE_DATA 2-341 LVTMA_FORCE_OUTPUT_CNTL 2-341 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-84 Proprietary...
  • Page 445 2-351 MAX_LATENCY 2-65 MAXX_PWM 2-152 MC_AGP_LOCATION MC_ARB_DRAM_PENALTIES MC_ARB_DRAM_PENALTIES2 MC_ARB_DRAM_PENALTIES3 MC_ARB_MIN MC_ARB_RATIO_CLK_SEQ MC_ARB_RDWR_SWITCH MC_ARB_TIMERS MC_CNTL0 MC_CNTL1 MC_DEBUG 2-32 MC_FB_LOCATION MC_GUI_DYN_CNTL 2-160 MC_HOST_DYN_CNTL 2-160 MC_IMP_CNTL 2-28 MC_IMP_DEBUG 2-28 MC_IMP_STATUS 2-28 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-85...
  • Page 446 MC_IO_WR_QS_CNTL_I1 2-27 MC_MISC_0 2-31 MC_MISC_1 2-31 MC_NPL_STATUS_I0 2-27 MC_NPL_STATUS_I1 2-27 MC_PMG_CFG 2-31 MC_PMG_CMD 2-31 MC_PT0_CLIENT0_CNTL 2-43 MC_PT0_CLIENT1_CNTL 2-43 MC_PT0_CLIENT10_CNTL 2-51 MC_PT0_CLIENT11_CNTL 2-52 MC_PT0_CLIENT12_CNTL 2-53 MC_PT0_CLIENT13_CNTL 2-54 MC_PT0_CLIENT14_CNTL 2-55 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-86 Proprietary...
  • Page 447 MC_PT0_CONTEXT2_FLAT_END_ADDR 2-40 MC_PT0_CONTEXT2_FLAT_START_ADDR 2-39 MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR 2-42 MC_PT0_CONTEXT3_CNTL 2-34 MC_PT0_CONTEXT3_DEFAULT_READ_ADDR 2-37 MC_PT0_CONTEXT3_FLAT_BASE_ADDR 2-38 MC_PT0_CONTEXT3_FLAT_END_ADDR 2-41 MC_PT0_CONTEXT3_FLAT_START_ADDR 2-39 MC_PT0_CONTEXT3_MULTI_LEVEL_BASE_ADDR 2-42 MC_PT0_CONTEXT4_CNTL 2-34 MC_PT0_CONTEXT4_DEFAULT_READ_ADDR 2-37 MC_PT0_CONTEXT4_FLAT_BASE_ADDR 2-38 MC_PT0_CONTEXT4_FLAT_END_ADDR 2-41 MC_PT0_CONTEXT4_FLAT_START_ADDR 2-39 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-87...
  • Page 448 2-161 MC_RBS_MAP 2-29 MC_RBS_MISC 2-30 MC_RBS_SUN_HWM 2-30 MC_RFSH_CNTL MC_SEQ_A_PAD_CNTL_I0 2-18 MC_SEQ_A_PAD_CNTL_I1 2-18 MC_SEQ_CAS_TIMING 2-11 MC_SEQ_CK_PAD_CNTL_I0 2-16 MC_SEQ_CK_PAD_CNTL_I1 2-16 MC_SEQ_CMD 2-19 MC_SEQ_CMD_PAD_CNTL_I0 2-17 MC_SEQ_CMD_PAD_CNTL_I1 2-17 MC_SEQ_DQ_PAD_CNTL_I0 2-17 MC_SEQ_DQ_PAD_CNTL_I1 2-17 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-88 Proprietary...
  • Page 449 MEM_BASE_HI 2-63 MEM_BASE_LO 2-63 MIN_GRANT 2-65 MM_DATA 2-58 MM_INDEX 2-58 MPLL_BYPASSCLK_SEL 2-157 MPLL_CLK_SEL 2-157 MPLL_CNTL_MODE 2-157 MPLL_FUNC_CNTL 2-156 MPLL_TIME 2-163 MSI_CAP_ID 2-69 MSI_MSG_ADDR_HI 2-70 MSI_MSG_ADDR_LO 2-70 MSI_MSG_CNTL 2-69 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-89...
  • Page 450 PCIE_LC_CNTL 2-95 PCIE_LC_FORCE_SYNC_LOSS_CNTL 2-97 PCIE_LC_LINK_WIDTH_CNTL 2-97 PCIE_LC_N_FTS_CNTL 2-95 PCIE_LC_STATE0 2-95 PCIE_LC_STATE1 2-96 PCIE_LC_STATE2 2-96 PCIE_LC_STATE3 2-96 PCIE_LC_STATE4 2-96 PCIE_LC_STATE5 2-96 PCIE_P_BUF_STATUS 2-98 PCIE_P_CNTL 2-97 PCIE_P_CNTL2 2-98 PCIE_P_DECODE_ERR_CNT_0 2-103 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-90 Proprietary...
  • Page 451 PCIE_PRBS23_BITCNT1 2-107 PCIE_PRBS23_BITCNT10 2-109 PCIE_PRBS23_BITCNT11 2-109 PCIE_PRBS23_BITCNT12 2-109 PCIE_PRBS23_BITCNT13 2-109 PCIE_PRBS23_BITCNT14 2-109 PCIE_PRBS23_BITCNT15 2-109 PCIE_PRBS23_BITCNT2 2-107 PCIE_PRBS23_BITCNT3 2-108 PCIE_PRBS23_BITCNT4 2-108 PCIE_PRBS23_BITCNT5 2-108 PCIE_PRBS23_BITCNT6 2-108 PCIE_PRBS23_BITCNT7 2-108 PCIE_PRBS23_BITCNT8 2-108 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-91...
  • Page 452 PCIE_RX_CREDITS_RECEIVED 2-93 PCIE_RX_CREDITS_RECEIVED_CPLD 2-93 PCIE_RX_CREDITS_RECEIVED_D 2-93 PCIE_RX_DLP_CRC 2-92 PCIE_RX_DLP0 2-92 PCIE_RX_DLP1 2-92 PCIE_RX_ERR_LOG 2-94 PCIE_RX_EXPECTED_SEQNUM 2-94 PCIE_RX_MAL_TLP_COUNT 2-93 PCIE_RX_NUM_NACK 2-91 PCIE_RX_NUM_NACK_GENERATED 2-91 PCIE_RX_TLP_CRC 2-92 PCIE_RX_TLP_HDR0 2-91 PCIE_RX_TLP_HDR1 2-91 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-92 Proprietary...
  • Page 453 PCIE_TX_GART_TLB12_DATA 2-86 PCIE_TX_GART_TLB13_DATA 2-86 PCIE_TX_GART_TLB14_DATA 2-86 PCIE_TX_GART_TLB15_DATA 2-86 PCIE_TX_GART_TLB16_DATA 2-87 PCIE_TX_GART_TLB17_DATA 2-87 PCIE_TX_GART_TLB18_DATA 2-87 PCIE_TX_GART_TLB19_DATA 2-87 PCIE_TX_GART_TLB2_DATA 2-84 PCIE_TX_GART_TLB20_DATA 2-87 PCIE_TX_GART_TLB21_DATA 2-87 PCIE_TX_GART_TLB22_DATA 2-88 PCIE_TX_GART_TLB23_DATA 2-88 PCIE_TX_GART_TLB24_DATA 2-88 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-93...
  • Page 454 PMI_CAP_ID 2-65 PMI_DATA 2-66 PMI_NXT_CAP_PTR 2-65 PMI_PMC_REG 2-66 PMI_STATUS 2-66 POLARITY_CNTL 2-163 REG_BASE_HI 2-64 REG_BASE_LO 2-63 REGPROG_INF 2-62 REVISION_ID 2-62 ROM_DATA 2-148 ROM_INDEX 2-148 SCLK_PWRMGT_CNTL 2-157 SEPROM_CNTL1 2-146 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-94 Proprietary...
  • Page 455 TMDSA_CRC_SIG_RGB 2-309 TMDSA_CTL_BITS 2-311 TMDSA_CTL0_1_GEN_CNTL 2-312 TMDSA_CTL2_3_GEN_CNTL 2-313 TMDSA_DATA_SYNCHRONIZATION 2-311 TMDSA_DCBALANCER_CONTROL 2-311 TMDSA_DEBUG 2-311 TMDSA_FORCE_DATA 2-307 TMDSA_FORCE_OUTPUT_CNTL 2-307 TMDSA_LOAD_DETECT 2-315 TMDSA_MACRO_CONTROL 2-315 TMDSA_RANDOM_PATTERN_SEED 2-310 TMDSA_RED_BLUE_SWITCH 2-311 TMDSA_REG_TEST_OUTPUT 2-316 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-95...
  • Page 456 VGA_STATUS_CLEAR 2-191 VGA_SURFACE_PITCH_SELECT 2-187 VGA_TEST_CONTROL 2-193 VID_BUFFER_CONTROL 2-133 VIDEOMUX_CNTL 2-145 VIP_DYN_CNTL 2-160 VIP_HW_DEBUG 2-148 VIPH_CH0_ABCNT 2-122 VIPH_CH0_ADDR 2-120 VIPH_CH0_DATA 2-120 VIPH_CH0_SBCNT 2-121 VIPH_CH1_ABCNT 2-122 VIPH_CH1_ADDR 2-121 VIPH_CH1_DATA 2-120 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-96 Proprietary...
  • Page 457 VIPH_CONTROL 2-122 VIPH_DMA_CHUNK 2-123 VIPH_DV_INT 2-124 VIPH_DV_LAT 2-123 VIPH_REG_ADDR 2-125 VIPH_REG_DATA 2-125 VIPH_TIMEOUT_STAT 2-124 VIPPAD_A 2-150 VIPPAD_EN 2-151 VIPPAD_MASK 2-150 VIPPAD_STRENGTH 2-148 VIPPAD_Y 2-151 VOL_DROP_CNT 2-164 ZV_LCDPAD_Y 2-148 © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary A-97...
  • Page 458 M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. A-98 Proprietary...

  • Page 459: Appendix B Revision History

    Rev 0.2 (Aug 05) • This document is based on the engineering document created on Aug 9. Rev 0.3 (Sept 05) • Added section “LVDS Registers” on page 2-340. © 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual Proprietary...
  • Page 460 This page intentionally left blank. M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc. Proprietary...

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