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Memory Controller Registers
CONTEXT_SELECTION_0
CONTEXT_SELECTION_1
SYSTEM_ACCESS_MODE
SYSTEM_APERTURE_UNMAPPED_ACCESS
EFFECTIVE_L1_CACHE_SIZE
ENABLE_FRAGMENT_PROCESSING
EFFECTIVE_L1_QUEUE_SIZE
ENABLE_PROTECTION_FAULTS
BYPASS_L2_CACHE
INVALIDATE_L1_TLB (W)
This register provides static control for Client 6 in Page Table Unit 0. There are currently 21 read clients and 12 write clients, so each Page Table
Unit will service roughly 17 clients.
M56 Register Reference Manual
2-48
4:2
0x0
context to use when interface context selection bit is 0. other than
system context, these assignments are suggestions only -- the driver
will determine actual assignments.
0=system
1=gpu
2=host
3=idct
7:5
0x0
context to use when interface context selection bit is 1. other than
system context, these assignments are suggestions only -- the driver
will determine actual assignments.
0=system
1=gpu
2=host
3=idct
9:8
0x0
values 1 and 2 are meaningful iff system context 0 itself is enabled
0=always physical access
1=always logical access via system context 0 page table
2=inside system aperture is mapped, outside is unmapped
3=inside system aperture is unmapped, outside is mapped
10
0x0
mapped accesses (inside aperture) always go through system con-
text 0 page table
0=pass through (physical access)
1=discard write, read from default address
13:11
0x3
(0...4) 2**(field) page table entries
14
0x0
0=off
1=on
17:15
0x3
(0...4) 2**(field) latency compensation queue entries
18
0x1
enable/disable protection fault processing for this client
0=disable
1=enable
19
0x0
bypass L2 cache to test L1 client functionality with effective identity
map
0=use L2 cache
1=bypass L2 cache test only
20
0x0
invalidate only the contents of the L1 TLB on rising edge
0=normal operation
1=invalidate L1 TLB
© 2007 Advanced Micro Devices, Inc.
Proprietary
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