AMD M56 Reference Manual page 111

DISPARITY_ERR_CNT_12
Receiver Decoder Error Counter for Lane 12
Field Name
CODE_ERR_CNT_13
DISPARITY_ERR_CNT_13
Receiver Decoder Error Counter for Lane 13
Field Name
CODE_ERR_CNT_14
DISPARITY_ERR_CNT_14
Receiver Decoder Error Counter for Lane 14
Field Name
CODE_ERR_CNT_15
DISPARITY_ERR_CNT_15
Receiver Decoder Error Counter for Lane 15
Field Name
ERR_REPORTING_DIS
SYM_UNLOCKED_EN
Error Control Registers
Field Name
BIFBUSY_DLY_SEL
GR_WHEN_LINK_DN_EN
GR_WHEN_HOT_RESET_EN
GR_DLY_SEL
PR_WHEN_LINK_DN_EN
PR_WHEN_HOT_RESET_EN
PR_DLY_SEL
© 2007 Advanced Micro Devices, Inc.
Proprietary
31:16
PCIE_P_DECODE_ERR_CNT_13 - R - 32 bits - PCIEIND:0xFD
Bits Default
15:0
31:16
PCIE_P_DECODE_ERR_CNT_14 - R - 32 bits - PCIEIND:0xFE
Bits Default
15:0
31:16
PCIE_P_DECODE_ERR_CNT_15 - R - 32 bits - PCIEIND:0xFF
Bits Default
15:0
31:16
PCIE_ERR_CNTL - RW - 32 bits - PCIEIND:0xE0
Bits Default
0
1
PCIE_CLK_RST_CNTL - RW - 32 bits - PCIEIND:0xE1
Bits Default
1:0
8
9
11:10
12
13
15:14
0x0 Disparity Error Counter
0x0 Decoder Error Counter
0x0 Disparity Error Counter
0x0 Decoder Error Counter
0x0 Disparity Error Counter
0x0 Decoder Error Counter
0x0 Disparity Error Counter
0x1 Disable PCI Express Advanced Error Reporting
0x0 Enable Reporting of Symbol Unlocked Errors
0x0 Select the delay to switch of the clock inside the PCIE blocks
0x0 Force Global reset when the link is down
0x1 Force Global reset when hot reset is active
0x0 Select the delay between link-down or hot-reset to the global reset
assertion
0=0 msec
1=4 msec
2=8 msec
3=16 msec
0x0 Force Phy layer (PL) reset when the link is down
0x1 DO NOT Force Phy reset (PL) when hot reset is active
0x0 Select the delay between link-down or hot-reset to the phy reset
assertion
0=0 msec
1=4 msec
2=8 msec
3=16 msec
Bus Interface Registers
Description
Description
Description
Description
Description
M56 Register Reference Manual
2-105