AMD M56 Reference Manual page 126

VIP/I2C Registers
I2C_INT (R)
I2C_INT_AK (W)
Reserved
VIPH_INT (R)
General Interrupt Status register.
These fields can be polled and acknowledged even if interrupts are disabled, or the respective fields are masked in the GEN_INT_CNTL register.
Field Name
VIPH_CH0_DT
VIPH0 data interface
Field Name
VIPH_CH1_DT
VIPH0 data interface
Field Name
VIPH_CH2_DT
VIPH0 data interface
Field Name
VIPH_CH3_DT
VIPH0 data interface
Field Name
VIPH_CH0_AD
VIPH0 command + address.
M56 Register Reference Manual
2-120
17 0x0
17 0x0
20 0x0
24 0x0
VIPH_CH0_DATA - RW - 32 bits - VIPDEC:0xC00
Bits Default
31:0 0x0
VIPH_CH1_DATA - RW - 32 bits - VIPDEC:0xC04
Bits Default
31:0 0x0
VIPH_CH2_DATA - RW - 32 bits - VIPDEC:0xC08
Bits Default
31:0 0x0
VIPH_CH3_DATA - RW - 32 bits - VIPDEC:0xC0C
Bits Default
31:0 0x0
VIPH_CH0_ADDR - RW - 32 bits - VIPDEC:0xC10
Bits Default
7:0 0x0
I2C interrupt.
0=No event
1=Event has occurred, interrupting if enabled
I2C interrupt acknowledge/reset.
0=No effect
1=Clear status
VIP host port interrupt.
0=No event
1=Event has occurred, interrupting if enabled
Description
VIPH0 data interface
Description
VIPH0 data interface
Description
VIPH0 data interface
Description
VIPH0 data interface
Description
Bit(3:0): FIFO address
Bit(4): 0= register access, 1 = FIFO access.
Bit(5): 0= register write, 1= register read.
Bits(7:6): Slave device ID.
© 2007 Advanced Micro Devices, Inc.
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