AMD M56 Reference Manual page 105

P_DESKEW_BUF_OVERFLOW_15
PHY BUFFER STATUS REGISTER
Field Name
P_DECODE_ERR_0
P_DECODE_ERR_1
P_DECODE_ERR_2
P_DECODE_ERR_3
P_DECODE_ERR_4
P_DECODE_ERR_5
P_DECODE_ERR_6
P_DECODE_ERR_7
P_DECODE_ERR_8
P_DECODE_ERR_9
P_DECODE_ERR_10
P_DECODE_ERR_11
P_DECODE_ERR_12
P_DECODE_ERR_13
P_DECODE_ERR_14
P_DECODE_ERR_15
P_DISPARITY_ERR_0
P_DISPARITY_ERR_1
P_DISPARITY_ERR_2
© 2007 Advanced Micro Devices, Inc.
Proprietary
31 0x0
PCIE_P_DECODER_STATUS - RW - 32 bits - PCIEIND:0xB3
Bits Default
0 0x0
1 0x0
2 0x0
3 0x0
4 0x0
5 0x0
6 0x0
7 0x0
8 0x0
9 0x0
10 0x0
11 0x0
12 0x0
13 0x0
14 0x0
15 0x0
16 0x0
17 0x0
18 0x0
Symbol skew buffer over/underflow: lane 15
Description
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the decoding error, i.e. Can't decode the
incoming data.
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the link error:
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the link error:
bit15 => Lane 15 (0 = OK, 1 = error), etc
Indicates which lane has the link error:
bit15 => Lane 15 (0 = OK, 1 = error), etc
M56 Register Reference Manual
Bus Interface Registers
2-99