Table of Contents
Advertisement
Field Name
GRPH_ROTATE
GRPH_FN_SEL
Data Rotate Register
Field Name
GRPH_RMAP
Read Map Select Register
Field Name
GRPH_WRITE_MODE
GRPH_READ1
CGA_ODDEVEN
GRPH_OES
GRPH_PACK
Graphics Mode Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
GRA03 - RW - 8 bits - VGAGRPHIND:0x3
Bits
Default
2:0
0x0
Rotate Count Bits 2-0. Specifies the number of bit positions that the
CPU data is to be rotated to the right, before doing the function
selected by bits 3 and 4 above and subsequent bit mask select and
write operations. Rotation is carried out only in write modes 0 and 3.
In these two modes, the CPU data is rotated first, the operated only
the function bits GRA03[4:3], the updated by the bit mask register
GRA05.
4:3
0x0
Function Select Bits 1 and 2. These functions are performed on the
CPU data before the selected bits are updated by the bit mask regis-
ter, and then written to the display buffers.
0=Replace
1=AND
2=OR
3=XOR
GRA04 - RW - 8 bits - VGAGRPHIND:0x4
Bits
Default
1:0
0x0
Read Mode 0 Only: GRA controller returns the contents of one of the
four latched buffer bytes to CPU each time a CPU read loads these
latches. The 2 bits (0 and 1) define a value that represents the bit
map where CPU is to read data - useful in transferring bit map data
between the maps and system RAM.
GRA05 - RW - 8 bits - VGAGRPHIND:0x5
Bits
Default
1:0
0x0
Write Mode:
0=Write mode 0
1=Write mode 1
2=Write mode 2
3=Write mode 3
3
0x0
Read Mode:
0=Read mode 0, byte oriented
1=Read mode 1, pixel oriented
4
0x0
Odd/Even Addressing Enable. Used to enable CGA emulation, this
bit enables off/even addressing mode when it is logical one. Nor-
mally, this bit and memory mode bit SEQ04[2] are set to agree with
each other in enabling odd/even mode emulation.
0=Disable Odd/Even Addressing
1=Enable Odd/Even Addressing
5
0x0
Shift Register Mode: This bit controls how data from memory is
loaded into the shift registers M0D0:M0D7, M1D0:M1D7;
M2D0:M2D7, and M3D0:M3D7 are representations of this data.
0=Linear shift mode
1=Tiled shift mode
6
0x0
256 Colour Mode. This bit also controls how data from memory is
loaded into the shift registers.
0=Use shift register mode as per GRPH_OES
1=256 color mode, read as packed pixels, ignore GRPH_OES
VGA Registers
Description
Description
Description
M56 Register Reference Manual
2-179
Advertisement
Table of Contents
