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CRTC Registers
D2CRTC_BLANK_DATA_EN
D2CRTC_BLANK_DE_MODE
Controls forced blanking of active area of display timing. Useful for display mode switches when corrupted image may be generated for a frame or
two.
Field Name
D2CRTC_INTERLACE_ENABLE
D2CRTC_INTERLACE_FORCE_NEXT_FIELD
(W)
Interlaced timing control for CRTC2
Field Name
D2CRTC_INTERLACE_CURRENT_FIELD (R)
D2CRTC_INTERLACE_NEXT_FIELD (R)
Read-only register reports the polarity of the current and next field for interlaced timing
Field Name
D2CRTC_BLANK_DATA_COLOR_BLUE_CB
D2CRTC_BLANK_DATA_COLOR_GREEN_Y
D2CRTC_BLANK_DATA_COLOR_RED_CR
Set the color for pixels in blank region
Field Name
D2CRTC_OVERSCAN_COLOR_BLUE
D2CRTC_OVERSCAN_COLOR_GREEN
D2CRTC_OVERSCAN_COLOR_RED
M56 Register Reference Manual
2-288
8
16
D2CRTC_INTERLACE_CONTROL - RW - 32 bits - DISPDEC:0x6888
Bits
0
17:16
D2CRTC_INTERLACE_STATUS - RW - 32 bits - DISPDEC:0x688C
Bits
0
1
D2CRTC_BLANK_DATA_COLOR - RW - 32 bits - DISPDEC:0x6890
Bits
9:0
19:10
29:20
D2CRTC_OVERSCAN_COLOR - RW - 32 bits - DISPDEC:0x6894
Bits
9:0
19:10
29:20
0x0
Enable for blanking active display area. The active area of display
that is forced will use the D2CRTC_BLACK_COLOR value.
This field is optionally double buffered with
D2CRTC_BLANK_DATA_DOUBLE_BUFFER_EN.
0 = disable blanking
1 = enable blanking
0x0
Determines whether BLANK and DATA_ACTIVE signal keeps tog-
gling when screen is blank
0 = toggles BLANK and DATA_ACTIVE
1 = keep BLANK active and DATA_ACTIVE inactive
Default
0x0
Enables interlaced timing
0 = Progressive timing
1 = Interlaced timing
0x0
One shot force next field polarity when written
00 = does not force next field
01 = force only next field to odd
10 = force only next field to even
11 = does not force next field
Default
0x0
Reports the polarity of current field
0 = even
1 = odd
0x0
Reports the polarity of the next field. Normally the opposite of the cur-
rent field. When D2CRTC_INTERLACE_FORCE_NEXT_FIELD is
used to force polarity of next field, then next field can match current
field.
0 = even
1 = odd
Default
0x0
B / Cb component
0x0
G / Y component
0x0
R / Cr component
Default
0x0
B or Cb component
0x0
G or Y component
0x0
R or Cr component
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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