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Table A-6 Display Registers Sorted by Address
LVTMA_FORCE_OUTPUT_CNTL
LVTMA_BIT_DEPTH_CONTROL
LVTMA_CONTROL0_FEEDBACK
LVTMA_STEREOSYNC_CTL_SEL
LVTMA_SYNC_CHAR_PATTERN_SEL
LVTMA_SYNC_CHAR_PATTERN_0_1
LVTMA_SYNC_CHAR_PATTERN_2_3
LVTMA_RANDOM_PATTERN_SEED
LVTMA_DCBALANCER_CONTROL
LVTMA_RED_BLUE_SWITCH
LVTMA_DATA_SYNCHRONIZATION
LVTMA_TRANSMITTER_ENABLE
LVTMA_TRANSMITTER_CONTROL
LVTMA_REG_TEST_OUTPUT
LVTMA_TRANSMITTER_DEBUG
© 2007 Advanced Micro Devices, Inc.
Proprietary
Register Name
DACB_PWR_CNTL
LVTMA_CNTL
LVTMA_SOURCE_SELECT
LVTMA_COLOR_FORMAT
LVTMA_FORCE_DATA
LVTMA_CONTROL_CHAR
LVTMA_CRC_CNTL
LVTMA_CRC_SIG_MASK
LVTMA_CRC_SIG_RGB
LVTMA_2ND_CRC_RESULT
LVTMA_TEST_PATTERN
LVTMA_DEBUG
LVTMA_CTL_BITS
LVTMA_CTL0_1_GEN_CNTL
LVTMA_CTL2_3_GEN_CNTL
LVTMA_PWRSEQ_REF_DIV
LVTMA_PWRSEQ_DELAY1
LVTMA_PWRSEQ_DELAY2
LVTMA_PWRSEQ_CNTL
LVTMA_PWRSEQ_STATE
LVTMA_BL_MOD_CNTL
LVTMA_LVDS_DATA_CNTL
LVTMA_MODE
LVTMA_LOAD_DETECT
LVTMA_MACRO_CONTROL
(Continued)
Address
DISPDEC:0x7A68
DISPDEC:0x7A80
DISPDEC:0x7A84
DISPDEC:0x7A88
DISPDEC:0x7A8C
DISPDEC:0x7A90
DISPDEC:0x7A94
DISPDEC:0x7A98
DISPDEC:0x7A9C
DISPDEC:0x7AA0
DISPDEC:0x7AA4
DISPDEC:0x7AA8
DISPDEC:0x7AAC
DISPDEC:0x7AB0
DISPDEC:0x7AB4
DISPDEC:0x7AB8
DISPDEC:0x7ABC
DISPDEC:0x7AC0
DISPDEC:0x7AC4
DISPDEC:0x7AC8
DISPDEC:0x7ACC
DISPDEC:0x7AD0
DISPDEC:0x7AD4
DISPDEC:0x7AD8
DISPDEC:0x7ADC
DISPDEC:0x7AE0
DISPDEC:0x7AE4
DISPDEC:0x7AE8
DISPDEC:0x7AEC
DISPDEC:0x7AF0
DISPDEC:0x7AF4
DISPDEC:0x7AF8
DISPDEC:0x7AFC
DISPDEC:0x7B00
DISPDEC:0x7B04
DISPDEC:0x7B08
DISPDEC:0x7B0C
DISPDEC:0x7B10
DISPDEC:0x7B14
DISPDEC:0x7B18
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M56 Register Reference Manual
A-37
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