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Field Name
GENMO_MONO_ADDRESS_B
(mirror of
GENMO_WT:GENMO_MONO_ADDRESS_B)
VGA_RAM_EN
(mirror of GENMO_WT:VGA_RAM_EN)
VGA_CKSEL
(mirror of GENMO_WT:VGA_CKSEL)
ODD_EVEN_MD_PGSEL
(mirror of
GENMO_WT:ODD_EVEN_MD_PGSEL)
VGA_HSYNC_POL
(mirror of GENMO_WT:VGA_HSYNC_POL)
VGA_VSYNC_POL
(mirror of GENMO_WT:VGA_VSYNC_POL)
Miscellaneous Output Register (Read)
Field Name
SEQ_IDX
SEQ Index Register
Field Name
SEQ_DATA
SEQ Data Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
GENMO_RD - R - 8 bits - DISPDEC:0x3CC
Bits
Default
0
0x0
VGA addressing mode.
1
0x0
Enables/Disables CPU access to video RAM at VGA aperture.
3:2
0x0
Selects pixel clock frequency to use.
5
0x0
This bit is used in odd/even display modes (A/N modes: 0, 1, 2, 3,
and 7). This bit is ignored when either bit GRA06[1] or SEQ4[3] are
enabled.
Used to determine if the VGA aperture maps into the lower (even) or
upper (odd) page of memory.
6
0x0
Determines polarity of horizontal sync (HSYNC) for VGA modes.
0 = HSYNC pulse active high
1 = HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400 (and 200)
and 480 line modes. Active high is normally used for 350 line modes.
7
0x0
Determines polarity of vertical sync (VSYNC) for VGA modes.
0 = VSYNC pulse active high
1 = VSYNC pulse active low
The convention of VGA is to use active high VSYNC for 400 (and
200) line modes. Active low is normally used for 350 and 480 line
modes.
SEQ8_IDX - RW - 8 bits - DISPDEC:0x3C4
Bits
Default
2:0
0x0
This index points to one of the sequencer registers (SEQ_) at I/O port
address 0x3C5, for the next SEQ read/write operation.
SEQ8_DATA - RW - 8 bits - DISPDEC:0x3C5
Bits
Default
7:0
0x0
SEQ data indirect access
Description
0=Monochrome emulation, regs at 0x3Bx
1=Color/Graphic emulation, regs at 0x3Dx
0=Disable
1=Enable
0=25.1744MHz (640 Pels)
1=28.3212MHz (720 Pels)
2=Reserved
3=Reserved
0=Selects odd (high) memory locations
1=Selects even (low) memory locations
Description
Description
M56 Register Reference Manual
VGA Registers
2-195
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