Capture Registers - AMD M56 Reference Manual

VIP/I2C Registers
2.4.3

Capture Registers

Registers to facilitate the capture of input video data
Field Name
FCP0_SRC_SEL
Capture Port FCP clock mux control
Field Name
CAP0_INT_ACTIVE (R)
DMA_VIPH0_INT (R)
DMA_VIPH0_INT_AK (W)
DMA_VIPH1_INT (R)
DMA_VIPH1_INT_AK (W)
DMA_VIPH2_INT (R)
DMA_VIPH2_INT_AK (W)
DMA_VIPH3_INT (R)
DMA_VIPH3_INT_AK (W)
I2C_INT (R)
I2C_INT_AK (W)
Reserved
VIPH_INT (R)
General Interrupt Status register.
These fields can be polled and acknowledged even if interrupts are disabled, or the respective fields are masked in the GEN_INT_CNTL register.
M56 Register Reference Manual
2-126
FCP_CNTL - RW - 32 bits - VIPDEC:0x910
Bits Default
2:0 0x4
GEN_INT_STATUS - RW - 32 bits - VIPDEC:0x104
Bits Default
8 0x0
12 0x0
12 0x0
13 0x0
13 0x0
14 0x0
14 0x0
15 0x0
15 0x0
17 0x0
17 0x0
20 0x0
24 0x0
Description
PCICLK,PCLK, PCLKb, HREF, GND, HREFb.
0=PCICLK
1=PCLK
2=PCLKb
3=HREF
4=GND
5=HREFb
Description
Capture port 0 has active interrupt(s).
0=Capture port 0 not source of any active interrupt
1=Capture port 0 has active interrupt(s)
VIP host port channel 0 DMA interrupt.
0=No event
1=Event has occurred, interrupting if enabled
VIP host port channel 0 DMA interrupt acknowledge/reset.
0=No effect
1=Clear status
VIP host port channel 1 DMA interrupt.
0=No event
1=Event has occurred, interrupting if enabled
VIP host port channel 1 DMA interrupt acknowledge/reset.
0=No effect
1=Clear status
VIP host port channel 2 DMA interrupt.
0=No event
1=Event has occurred, interrupting if enabled
VIP host port channel 2 DMA interrupt acknowledge/reset.
0=No effect
1=Clear status
VIP host port channel 3 DMA interrupt.
0=No event
1=Event has occurred, interrupting if enabled
VIP host port channel 3 DMA interrupt acknowledge/reset.
0=No effect
1=Clear status
I2C interrupt.
0=No event
1=Event has occurred, interrupting if enabled
I2C interrupt acknowledge/reset.
0=No effect
1=Clear status
VIP host port interrupt.
0=No event
1=Event has occurred, interrupting if enabled
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