Table of Contents
Advertisement
Field Name
TMDSA_PLL_ENABLE
TMDSA_PLL_RESET
TMDSA_PLL_ENABLE_HPD_MASK
TMDSA_IDSCKSEL
TMDSA_PLL_PWRUP_SEQ_EN
TMDSA_TMCLK
TMDSA_TMCLK_FROM_PADS
TMDSA_TDCLK
TMDSA_TDCLK_FROM_PADS
TMDSA_BYPASS_PLL
TMDSA_INPUT_TEST_CLK_SEL
Field Name
TMDSA_REG_TEST_OUTPUT (R)
TMDSA_TEST_CNTL
© 2007 Advanced Micro Devices, Inc.
Proprietary
TMDSA_TRANSMITTER_CONTROL - RW - 32 bits - DISPDEC:0x7910
Bits
0
1
3:2
4
6
12:8
13
14
15
28
31
TMDSA_REG_TEST_OUTPUT - RW - 32 bits - DISPDEC:0x7914
Bits
9:0
18:16
Default
0x0
TMDSA transmitter's PLL enable. This can power down the PLL.
0=Disable
1=Enable
0x1
TMDSA transmitter's PLL reset. PLL will start the locking acquisition
process once this becomes low.
0x0
Determines whether result from HPD circuit can override
TMDSA_PLL_ENABLE and TMDSA_PLL_RESET
Bit 0: Set to 1 to enable override on disconnect
Bit 1: Set to 1 to enable override on connect.
0=Result from HPD circuit can not override TMDSA_PLL_ENABLE
1=Result from HPD circuit overrides TMDSA_PLL_ENABLE on dis-
connect
2=Result from HPD circuit overrides TMDSA_PLL_ENABLE on
connect
3=Result from HPD circuit overrides TMDSA_PLL_ENABLE
0x1
0=TMDS Transmitter uses pclk_tmdsa (IPIXCLK)
1=TMDS Transmitter uses pclk_tmdsa_direct (IDCLK)
0x0
Enable hardware delay of PLL enable / reset on power up / down to
match macro timing requirements. When
TMDSA_PLL_PWRUP_SEQ_EN=1, PLL will be reset 1 us before
PLL enable is deasserted, and PLL reset will be asserted for 10 us
after PLL enable is asserted. This timing is provided to match the
TMDS macro timing specification.
0=Disabled
1=Delay Enable/ Reset for clean PLL power up/down
0x0
For macro debug only
0x0
Controls input to ITMCLK pin on macro for macro debug only
0=Input to ITMCLK pins on macro come from TMDSA_TMCLK field
1=Input to ITMCLK pins on macro come from pads
0x0
For macro debug only
0x0
Controls input to ITDCLK pin on macro for macro debug only
0=Input to ITDCLK pin on macro comes from TMDSA_TDCLK field
1=Input to ITDCLK pin on macro comes from pads
0x1
Controls ICHCSEL pin on TMDSA macro
0: Coherent mode: transmitted clock is PLL output
1: Incoherent mode: transmitted clock is PLL input
0x0
Controls ITCLKSEL pin on TMDSA macro
Default
0x0
Outputs of the 10 shift registers (OTDATX[9:0]) from one of the chan-
nels during test mode.
0x0
Selects which of six register test output channels from TMDSA macro
is visible in TMDSA_REG_TEST_OUTPUT.
0=OTDAT0
1=OTDAT1
2=OTDAT2
3=OTDAT3
4=OTDAT4
5=OTDAT5
6=OTDAT0
7=OTDAT0
Display Output Registers
Description
Description
M56 Register Reference Manual
2-315
Advertisement
Table of Contents
