Related Manuals for AMD 3200 - Athlon 64 2.0 GHz Processor
Summary of Contents for AMD 3200 - Athlon 64 2.0 GHz Processor
- Page 1 Revision Guide for AMD Family Models h- Fh Processors Publication # 48063 Revision: 3.18 Issue Date: October 2012 Advanced Micro Devices...
- Page 2 No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Except as set forth in AMD's Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not...
- Page 3 October Revision Guide for AMD Family h Models h- Fh Processors List of Figures Figure Format of CPUID Fn List of Figures...
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Page 4: Table Of Contents
Revision Guide for AMD Family h Models h- Fh Processors October List of Tables Table Arithmetic and Logic Operators Table CPUID Values for AMD Family h Models h- Fh G r Processor Revisions Table CPUID Values for AMD Family h Models... -
Page 5: Revision History
October Revision Guide for AMD Family h Models h- Fh Processors Revision History Date Revision Description October Added AMD Opteron™ Series Series Series Processors and OR-C silicon revision to Overview and Tables - Added Mixed Processor Revision Support Added errata... - Page 6 Revision Guide Policy Occasionally AMD identifies product errata that cause the processor to deviate from published specifications Descriptions of identified product errata are designed to assist system and software designers in using the...
- Page 7 In order to define errata workarounds it is sometimes necessary to reference processor registers References to BIOS and Kernel registers in this document use a mnemonic notation consistent with that defined in the Developer's Guide BKDG for AMD Family h Models h- Fh Processors order...
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Page 8: Table Arithmetic And Logic Operators
Revision Guide for AMD Family h Models h- Fh Processors October NBPMCxXXX Y northbridge performance monitor events XXX is the hexadecimal event counter number programmed into MSRC EventSelect NB PERF CTL bits Y when specified signifies the unit mask programmed into MSRC... -
Page 9: Table Cpuid Values For Amd Family
October Revision Guide for AMD Family h Models h- Fh Processors Processor Identification This section shows how to determine the processor revision program and display the processor name string and construct the processor name string Revision Determination A processor revision is identified using a unique value that is returned in the EAX register after executing the... -
Page 10: Table Cpuid Values For Amd Family
Revision Guide for AMD Family h Models h- Fh Processors October Table CPUID Values for AMD Family h Models h- Fh C r Processor Revisions CPUID Fn EAX D F x Mnemonic F h b OR-B b OR-C Table CPUID Values for AMD Family... -
Page 11: Table Supported Mixed Revision Configurations
It is common practice for the BIOS to display the processor name string and model number whenever it displays processor information during boot up Motherboards that do not program the proper processor name string and model number will not pass AMD Note... - Page 12 Revision Guide for AMD Family h Models h- Fh Processors October Read D F x x D F x and write this value to MSRC Read D F x x D F x and write this value to MSRC Read D F x...
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Page 13: Table Cross Reference Of Product Revision To Osvw Id
October Revision Guide for AMD Family h Models h- Fh Processors Operating System Visible Workarounds This section describes how to identify operating system visible workarounds MSRC OS Visible Work-around MSR OSVW ID Length Architecture Programmer's Manual Volume System Programming order... -
Page 14: Table Cross-Reference Of Processor Revision To Errata
Revision Guide for AMD Family h Models h- Fh Processors October Product Errata This section documents product errata for the processors A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels This table cross-references the revisions of the part to each erratum "No fix planned"... - Page 15 October Revision Guide for AMD Family h Models h- Fh Processors Table Cross-Reference of Processor Revision to Errata continued CPUID Fn EAX D F x Errata Description P-state Limit Changes May Not Generate Interrupts No fix planned Non-Posted Reads May Block Write Dependent on Probe...
- Page 16 Revision Guide for AMD Family h Models h- Fh Processors October Table Cross-Reference of Processor Revision to Errata continued CPUID Fn EAX D F x Errata Description Processors Using MB L Subcaches May Execute a No fix planned Write-Back Invalidate Operation Incorrectly...
- Page 17 October Revision Guide for AMD Family h Models h- Fh Processors Table Cross-Reference of Processor Revision to Errata continued CPUID Fn EAX D F x Errata Description Processor May Incorrectly Report Cache Sharing Property in CPUID Topology One Core May Observe a Time Stamp Counter Skew...
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Page 18: Table Cross-Reference Of Errata To Package Type
Revision Guide for AMD Family h Models h- Fh Processors October Cross-Reference of Errata to Package Type This table cross-references the errata to each package type "X" signifies that the erratum applies to the package type An empty cell signifies that the erratum does not apply An erratum may not apply to a package type due to... - Page 19 October Revision Guide for AMD Family h Models h- Fh Processors Table Cross-Reference of Errata to Package Type continued Package Cross-Reference of Errata to Package Type...
- Page 20 Revision Guide for AMD Family h Models h- Fh Processors October Table Cross-Reference of Errata to Package Type continued Package Cross-Reference of Errata to Package Type...
- Page 21 October Revision Guide for AMD Family h Models h- Fh Processors Cross-Reference of Errata to Processor Segments This table cross-references the errata to each processor segment "X" signifies that the erratum applies to the processor segment An empty cell signifies that the erratum does not apply An erratum may not apply to a...
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Page 22: Table Cross-Reference Of Errata To Processor Segments
Revision Guide for AMD Family h Models h- Fh Processors October Table Cross-Reference of Errata to Processor Segments continued Processor Segment Cross-Reference of Errata to Processor Segments... - Page 23 October Revision Guide for AMD Family h Models h- Fh Processors Table Cross-Reference of Errata to Processor Segments continued Processor Segment Cross-Reference of Errata to Processor Segments...
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Page 24: Breakpoint Due To An Instruction That Has An Interrupt
Revision Guide for AMD Family h Models h- Fh Processors October Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost Description A DB exception occurring in guest mode may be discarded under the following conditions A trap-type DB exception is generated in guest mode during execution of an instruction with an interrupt... -
Page 25: Apic Task-Priority Register May Be Incorrect
October Revision Guide for AMD Family h Models h- Fh Processors APIC Task-Priority Register May Be Incorrect Description An APIC task priority register TPR write may use an incorrect internal buffer for the data Potential Effect on System Incorrect interrupt prioritization... -
Page 26: Corrected L Errors May Lead To System Hang
Revision Guide for AMD Family h Models h- Fh Processors October Corrected L Errors May Lead to System Hang Description Under a highly specific and detailed set of internal timing conditions that involves corrected L errors a processor read from the L cache may hang... -
Page 27: Scrub Rate Control Register Address Depends On Dctcfgsel
October Revision Guide for AMD Family h Models h- Fh Processors Scrub Rate Control Register Address Depends on DctCfgSel Description When DCT Configuration Select DctCfgSel D F x C is b accesses to the Scrub Rate Control register D F x... -
Page 28: Some Lightweight Profiling Counters Stop Counting When
Revision Guide for AMD Family h Models h- Fh Processors October Some Lightweight Profiling Counters Stop Counting When Instruction-Based Sampling is Enabled Description When Lightweight Profiling LWP and Instruction-Based Sampling IBS measurement of instruction execution are simultaneously enabled the following LWP counters do not increment... -
Page 29: Lightweight Profiling May Not Indicate Fused Branch
October Revision Guide for AMD Family h Models h- Fh Processors Lightweight Profiling May Not Indicate Fused Branch Description The Lightweight Profiling LWP fused operation bit FUS - bit of the branch retired event record LWP EventId may not be set when the processor core is profiling a fused branch a compare operation followed by... -
Page 30: Performance Counter For Instruction Cache Misses Does
Revision Guide for AMD Family h Models h- Fh Processors October Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches Description PMCx Instruction Cache Misses does not increment for L instruction cache misses that are due to... -
Page 31: Performance Counter For Ineffective Software Prefetches
October Revision Guide for AMD Family h Models h- Fh Processors Performance Counter for Ineffective Software Prefetches Does Not Count for L Hits Description PMCx ineffective software prefetch due to an L cache hit does not increment Potential Effect on System... -
Page 32: Performance Counter Does Not Count For Some Retired Micro-Ops
Revision Guide for AMD Family h Models h- Fh Processors October Performance Counter Does Not Count for Some Retired Micro-Ops Description Some instructions with F h in the opcode byte are incorrectly detected by the processor core as empty micro-... -
Page 33: Gart Table Walk Probes May Cause System Hang
October Revision Guide for AMD Family h Models h- Fh Processors GART Table Walk Probes May Cause System Hang Description Probes that are generated for GART table walks may overflow internal queues and lead to a deadlock Potential Effect on System... -
Page 34: Latency Performance Counters Are Not Accurate
Revision Guide for AMD Family h Models h- Fh Processors October Latency Performance Counters Are Not Accurate Description Latency performance counters NBPMCx E through NBPMCx E are not accurate when L speculative miss prefetching is enabled D F x B... -
Page 35: Incorrect Memory Controller Operation Due To A
ECC byte lane and all populated DIMMs b BIOS should set DataTxFifoWrDly D F x bits BIOS and Kernel Developer's Guide BKDG for AMD Family h Models h- Fh as specified in the Processors order... -
Page 36: A Far Control Transfer Changing Processor Operating
Revision Guide for AMD Family h Models h- Fh Processors October A Far Control Transfer Changing Processor Operating Mode May Generate a False Machine Check Description A far control transfer that changes the processor operating mode may erroneously indicate a decoder instruction... -
Page 37: Vpextrq And Vpinsrq May Not Signal Invalid-Opcode Exception
October Revision Guide for AMD Family h Models h- Fh Processors VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception Description Advanced Vector Extensions AVX variants of legacy SSE instructions normally promote the size of a GPR operand using VEX W When running in... -
Page 38: Last-Branch Record Enabled May Cause Machine Check
Revision Guide for AMD Family h Models h- Fh Processors October Last-Branch Record Enabled May Cause Machine Check and Incorrect LastBranchToIp Description When LBR is enabled a complex interaction between two threads of the same compute-unit may result in the... -
Page 39: Hypertransport ™ Link Retry Due To Partial Crc Error
October Revision Guide for AMD Family h Models h- Fh Processors ™ HyperTransport Link Retry Due to Partial CRC Error May Cause System Hang Description The northbridge may stall when a probe hit returning data occurs simultaneously with a link retry due to a partial CRC error detected on an unrelated read packet This error can only occur on a coherent HyperTransport ™... -
Page 40: Hypertransport ™ Link Frequency Changes May Cause A
Revision Guide for AMD Family h Models h- Fh Processors October ™ HyperTransport Link Frequency Changes May Cause a System Hang Description A HyperTransport ™ link operating at a Gen frequency greater than GT s may have excessive link retries... -
Page 41: P-State Limit Changes May Not Generate Interrupts
October Revision Guide for AMD Family h Models h- Fh Processors P-state Limit Changes May Not Generate Interrupts Description P-state limit changes fail to generate interrupts when the target P-state limit is a higher or equal performance P- state lower or equal numbered P-state than the Application Power Management APM P-state limit... -
Page 42: Non-Posted Reads May Block Write Dependent On Probe Responses
Revision Guide for AMD Family h Models h- Fh Processors October Non-Posted Reads May Block Write Dependent on Probe Responses Description The northbridge may stall indefinitely on non-posted reads when a posted write becomes dependent on probe responses Potential Effect on System... -
Page 43: Small Code Segment Limits May Cause Incorrect Limit Faults
October Revision Guide for AMD Family h Models h- Fh Processors Small Code Segment Limits May Cause Incorrect Limit Faults Description In cases where the code segment limit is less than h and the Granularity G bit is zero the processor... -
Page 44: Sb-Rmi Processor State Accesses May Persistently
Revision Guide for AMD Family h Models h- Fh Processors October SB-RMI Processor State Accesses May Persistently Timeout if Interrupted by a Warm Reset Description The assertion of a warm reset during a small timing window of an APML SB-RMI processor state access may... -
Page 45: Sb-Rmi Writes May Not Be Observed By Processor
October Revision Guide for AMD Family h Models h- Fh Processors SB-RMI Writes May Not Be Observed by Processor Description After a write using the APML SB-RMI interface to either the Inbound Message Registers SBRMI x F Software Interrupt Register SBRMI x... -
Page 46: Instruction Addresses Near Canonical Address Limit May Cause Gp Exception
Revision Guide for AMD Family h Models h- Fh Processors October Instruction Addresses Near Canonical Address Limit May Cause GP Exception Description The processor may incorrectly generate a GP exception when an instruction executes within a small window of the linear-memory address at the limit of canonical address space... -
Page 47: Processor Does Not Report The Correct Dram Address For Mca Errors Within The Cc Save Area
October Revision Guide for AMD Family h Models h- Fh Processors Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC Save Area Description While reporting an ECC machine check error in the core C save area the processor may store an internal... - Page 48 Revision Guide for AMD Family h Models h- Fh Processors October containing the DRAM Base System Address from the node that reported the machine check The register contents from this step are saved in a temporary variable for use in the next step...
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Page 49: Mc Status Enable Bit Not Set When Logging Corrected Errors
October Revision Guide for AMD Family h Models h- Fh Processors MC STATUS Enable Bit Not Set When Logging Corrected Errors Description The processor does not set MC STATUS En b MSR when logging an enabled and corrected error in the IF machine check register bank bank... -
Page 50: Cpuid Incorrectly Reports Large Page Support In L Instruction Tlb
Revision Guide for AMD Family h Models h- Fh Processors October CPUID Incorrectly Reports Large Page Support in L Instruction TLB Description The CPUID instruction incorrectly reports the number of entries and the associativity of MB MB and GB TLB entries in the L instruction TLB... -
Page 51: Vmcb Interrupt Shadow Status May Be Incorrect
The SVM guest may continue to operate under interrupt shadow until the Move String instruction has completed This may delay servicing of a pending interrupt Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned Product Errata... -
Page 52: Aperf May Increase Unpredictably
Potential Effect on System Software may calculate the effective frequency of a core incorrectly or observe that the APERF register value appears to increase unpredictably Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned Product Errata... -
Page 53: P-State Limit And Stop Clock Assertion May Cause System Hang
S sleep state transition or a system hang if it occurs while another processor core is transitioning to the Core C state Potential Effect on System System hang Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata... -
Page 54: Local Interrupts Lint Lint May Occur While Apic Is
Revision Guide for AMD Family h Models h- Fh Processors October Local Interrupts LINT LINT May Occur While APIC is Software Disabled Description The processor unmasks local interrupts LINT and LINT while the APIC is software disabled Spurious- Interrupt Vector Register APICSWEn APICF... -
Page 55: Processor May Generate Incorrect P-State Limit Interrupts
October Revision Guide for AMD Family h Models h- Fh Processors Processor May Generate Incorrect P-state Limit Interrupts Description P-state limit changes due to SB-RMI SBI P-state Limit PstateLimit MSRC software Software P-state Limit Register SwPstateLimit D F x or hardware thermal control entering... -
Page 56: Load Operation May Receive Incorrect Data After Floating-Point Exception
FSW ES If these conditions are not met a load operation may receive data that was not updated by the most current write from a processor core AMD has not observed this erratum with any commercially available software... -
Page 57: Debug Breakpoint On Misaligned Store May Cause System Hang
System hang Suggested Workaround Contact your AMD representative for information on a BIOS update This workaround has a performance impact when certain debug breakpoints are enabled System developers that wish to enable debug breakpoints without this workaround may first set MSRC b AMD recommends this workaround be enabled with ™... -
Page 58: Svm Guest Performance Counters May Be Inaccurate Due To Smi
Performance monitoring software overcounts events for an SVM guest when non-intercepted SMIs occur Suggested Workaround Contact your AMD representative for information on a BIOS update When the workaround is enabled the processor swaps the HostGuestOnly bits i e bits of MSRC... -
Page 59: Misaligned Page Crossing String Operations May Cause System Hang
GB or MB which requires an address translation due to a TLB miss Potential Effect on System Unpredictable system behavior likely leading to a system hang Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned Product Errata... -
Page 60: Processor May Cache Prefetched Data From Remapped Memory Region
Revision Guide for AMD Family h Models h- Fh Processors October Processor May Cache Prefetched Data from Remapped Memory Region Description Prefetches from a write back WB DRAM memory region may persist when that memory region is remapped to an uncacheable UC or write combining WC memory type... -
Page 61: Instructions Performing Read-Modify-Write May Alter
October Revision Guide for AMD Family h Models h- Fh Processors Instructions Performing Read-Modify-Write May Alter Architectural State Before PF Description An instruction performing a read-modify-write operation may be presented with a page fault PF after modifying architectural state Potential Effect on System... -
Page 62: Some Processor Cores May Have Inaccurate Instruction
Revision Guide for AMD Family h Models h- Fh Processors October Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter Description The processor may over-report PMCx instruction cache fetches when the performance monitor is enabled on an odd processor core number APIC... -
Page 63: Am R Six Core Processor May Limit P-State When Core
Suggested Workaround AMD recommends that CC is enabled This erratum does not apply in this case and no workaround is necessary In the event that system software disables CC disable APM using Core Performance Boost Control... -
Page 64: Northbridge Fifo Read Write Pointer Overlap May Cause
Revision Guide for AMD Family h Models h- Fh Processors October Northbridge FIFO Read Write Pointer Overlap May Cause Hang or Protocol Error Machine Check Description A command or data transfer may be lost when the write pointer overlaps the read pointer of a synchronization... - Page 65 D F x C Dh or Eh Potential Effect on System Unpredictable system behavior This has only been observed by AMD as a system hang while using cache as general storage during boot Suggested Workaround Contact your AMD representative for information on a BIOS update...
- Page 66 Revision Guide for AMD Family h Models h- Fh Processors October Performance Counter May Incorrectly Count MXCSR Loads Description The processor may incorrectly increment the following performance counter due to XRSTOR FXRSTOR LDMXCSR or VLDMXCSR instructions loading the MXCSR register...
- Page 67 October Revision Guide for AMD Family h Models h- Fh Processors IBS Sampling of Instruction Fetches May Be Uneven Description Instructions selected for instruction-based sampling IBS of fetch performance Fetch Control IbsFetchEn MSRC b may be sampled unevenly when the instruction fetch stream is redirected e g due to...
- Page 68 None expected during normal operation A stack limit fault while executing an FNSAVE or FSAVE instruction is unusual and AMD has not observed the above conditions in any commercially available software In the unlikely event that software creates the conditions described above one of the following may occur...
- Page 69 When the address is actually a non-cacheable memory type the processor may incorrectly cache the data resulting in unpredictable system behavior AMD has only observed a northbridge link protocol error machine check The incorrect caching of an uncacheable memory region has not been observed by AMD...
- Page 70 Under a highly specific and detailed set of internal timing conditions the processor may store an incorrect instruction pointer rIP while processing an interrupt or a debug trap exception Potential Effect on System Unpredictable system behavior Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata...
- Page 71 October Revision Guide for AMD Family h Models h- Fh Processors Performance Counter for Locked Operations May Count Cycles from Non-Locked Operations Description PMCx may include cycles spent performing non-locked operations Potential Effect on System Performance monitoring software may receive an incorrect larger count of the number of cycles spent in the...
- Page 72 If the software was to perform a write to the TSC before this event the offset error is also removed Potential Effect on System None expected under normal circumstances Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata...
- Page 73 HTC-active state i e PROCHOT assertion Potential Effect on System Processor performance is limited to the lowest-performing P-state Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata...
- Page 74 DRAM address maps are not yet completed by BIOS the northbridge may flag a protocol error if it cannot find a DRAM address map associated with the BIOS access AMD has only observed this issue when node-interleaving is enabled DRAM Base Limit Register IntlvEn D F x...
- Page 75 October Revision Guide for AMD Family h Models h- Fh Processors Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling IBS is enabled in the following cases When IBS Op Data Register IbsDcMiss MSRC...
- Page 76 Revision Guide for AMD Family h Models h- Fh Processors October Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling IBS is enabled in the following cases The processor may set IBS Op Data Register IbsDcStToLdCan IbsDcStToLdFwd MSRC...
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Page 77: Maximum Value
IBS sample by writing to MSRC In the event that system software consistently writes to MSRC it is possible that the IBS fetch counter never expires and no instruction fetches are tagged AMD has not observed this effect with production software Suggested Workaround None... - Page 78 In the event that system software uses "STI RET" instead of a single IRET instruction or changes the stack segment simultaneously with the stack pointer i e not using a flat segment for the stack unpredictable system failure may result AMD has not observed this erratum with any commercially available software...
- Page 79 In addition it is possible for unpredictable system operation to occur without a machine check exception For example a processor core may not observe a write that is performed by another processor core AMD has not observed this effect in any commercially available software...
- Page 80 Revision Guide for AMD Family h Models h- Fh Processors October Incorrect APIC Remote Read Behavior Description The processor may provide incorrect APIC register data on an APIC remote register read A remote read is performed using Interrupt Command Register Low MsgType of...
- Page 81 October Revision Guide for AMD Family h Models h- Fh Processors Processor May Report Incorrect MCA Address for Loads that Cross Address Boundaries Description In the event that a line fill error or system read data error is reported for some but not all bytes of an unaligned...
- Page 82 Revision Guide for AMD Family h Models h- Fh Processors October Processor Core May Hang During CC Resume Description During a resume from core C state the processor may hang Potential Effect on System Processor core hang usually resulting in a system hang...
- Page 83 CPUs the processor may store incorrect data to the virtual machine control block VMCB reserved and guest save areas and may also store outside of the VMCB Potential Effect on System Data corruption Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata...
- Page 84 Revision Guide for AMD Family h Models h- Fh Processors October Processor Does Not Check -bit Canonical Address Boundary Case on Logical Address Description The processor core may not detect a GP exception if the processor is in -bit mode and the logical address of a...
- Page 85 October Revision Guide for AMD Family h Models h- Fh Processors Processor May Read Branch Status Register With Inconsistent Parity Bit Description Under a highly specific and detailed set of internal timing conditions the processor may read an internal branch...
- Page 86 LWP is enabled once software executes an LLWCP or XRSTOR instruction with a valid LWP control block LWPCB address Potential Effect on System System hang Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned No fix planned Product Errata...
- Page 87 BIOS should complete all writes to any register in the range of D F x C x through D F x C x D F FFFF dct prior to enabling DRAM scrubbing Specifically the writes that are BIOS and Kernel Developer's Guide BKDG for AMD Family h Models h- Fh recommended by the Processors order section "DRAM Phy Power Savings"...
- Page 88 Revision Guide for AMD Family h Models h- Fh Processors October Processor CC May Not Restore Trap Registers Description Following a core C power state transition the processor core may not restore the following registers MSRC IO Trap Register MSRC...
- Page 89 October Revision Guide for AMD Family h Models h- Fh Processors Processor May Incorrectly Report Cache Sharing Property in CPUID Topology Description On processor models that have a single core per compute-unit Compute Unit Status Register DualCore D F x...
- Page 90 In this sequence of events the thread may observe a TSC that appears to decrement In addition software may calculate a higher effective frequency APERF MSR E divided by MPERF Suggested Workaround Contact your AMD representative for information on a BIOS update Fix Planned Product Errata...
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Page 91: Documentation Support
Advanced Platform Management Link APML Specification order ™ HyperTransport I O Link Specification www hypertransport org AMD I O Virtualization Technology IOMMU Specification order See the AMD Web site at www amd com for the latest updates to documents Documentation Support...
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