AMD M56 Reference Manual page 421

Table A-13 VIP Registers Sorted by Address
CAP0_PORT_MODE_CNTL
CAP0_ANC_H_WINDOW
CAP0_VIDEO_SYNC_TEST
CAP0_ONESHOT_BUF_OFFSET
CAP0_ANC_BUF01_BLOCK_CNT
CAP0_ANC_BUF23_BLOCK_CNT
DMA_VIPH0_COMMAND
DMA_VIPH0_COMMAND
DMA_VIPH1_COMMAND
DMA_VIPH2_COMMAND
DMA_VIPH3_COMMAND
DMA_VIPH_MISC_CNTL
DMA_VIPH_CHUNK_1_VAL
DMA_VIP0_TABLE_ADDR
DMA_VIP1_TABLE_ADDR
DMA_VIP2_TABLE_ADDR
DMA_VIP3_TABLE_ADDR
© 2007 Advanced Micro Devices, Inc.
Proprietary
Register Name
CAP0_TRIG_CNTL
CAP0_DEBUG
CAP0_CONFIG
CAP0_ANC0_OFFSET
CAP0_ANC1_OFFSET
CAP0_BUF_STATUS
I2C_DATA
CAP0_VBI2_OFFSET
CAP0_VBI3_OFFSET
CAP0_ANC2_OFFSET
CAP0_ANC3_OFFSET
DMA_VIPH_STATUS
DMA_VIPH_CHUNK_0
DMA_VIPH0_ACTIVE
DMA_VIPH1_ACTIVE
DMA_VIPH2_ACTIVE
DMA_VIPH3_ACTIVE
ROM_INDEX
DMA_VIPH_ABORT
ROM_DATA
VIPH_CH0_DATA
VIPH_CH1_DATA
VIPH_CH2_DATA
VIPH_CH3_DATA
VIPH_CH0_ADDR
VIPH_CH1_ADDR
VIPH_CH2_ADDR
VIPH_CH3_ADDR
VIPH_CH0_SBCNT
(Continued)
Address
VIPDEC:0x94C
VIPDEC:0x950
VIPDEC:0x954
VIPDEC:0x958
VIPDEC:0x95C
VIPDEC:0x960
VIPDEC:0x964
VIPDEC:0x968
VIPDEC:0x96C
VIPDEC:0x970
VIPDEC:0x974
VIPDEC:0x97C
VIPDEC:0x98
VIPDEC:0x980
VIPDEC:0x984
VIPDEC:0x988
VIPDEC:0x98C
VIPDEC:0xA00
VIPDEC:0xA00
VIPDEC:0xA04
VIPDEC:0xA08
VIPDEC:0xA0C
VIPDEC:0xA10
VIPDEC:0xA14
VIPDEC:0xA18
VIPDEC:0xA1C
VIPDEC:0xA20
VIPDEC:0xA24
VIPDEC:0xA30
VIPDEC:0xA34
VIPDEC:0xA40
VIPDEC:0xA44
VIPDEC:0xA50
VIPDEC:0xA54
VIPDEC:0xA8
VIPDEC:0xA88
VIPDEC:0xAC
VIPDEC:0xC00
VIPDEC:0xC04
VIPDEC:0xC08
VIPDEC:0xC0C
VIPDEC:0xC10
VIPDEC:0xC14
VIPDEC:0xC18
VIPDEC:0xC1C
VIPDEC:0xC20
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M56 Register Reference Manual
A-61