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AMD SP5100 Manuals
Manuals and User Guides for AMD SP5100. We have
1
AMD SP5100 manual available for free PDF download: Data Book
AMD SP5100 Data Book (90 pages)
Brand:
AMD
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Revision History
3
Table of Contents
4
1 Introduction
8
Features of the SP5100
8
Part Number and Branding
11
Figure 1-1: SP5100 Rev A14 Branding Diagram
11
Figure 1-2: SP5100 Rev A15 Branding Diagrams
12
Table 1-1: SP5100 Part Numbers
12
2 SP5100 Block Diagram
13
Figure 2-1: SP5100 Block Diagram Showing the Internal PCI Devices and Major Function Blocks
13
3 SP5100 Power on Sequence and Timing
14
Power up and down Sequences
14
Table 3-1: SP5100 Power Up/Down Sequence Timing
14
Figure 3-1: SP5100 Power Up/Down Sequence
15
Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence
16
Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ
17
Figure 3-4: Timing for SB PWR_GOOD De-Asserted to RSMRST# De-Asserted
18
Figure 3-5: Timing for LDT_STP# Assertion on First Power up (G3 S5)
18
Figure 3-6: S5_3.3V Power down Sequence Requirement
19
4 SP5100 Strap Information
20
Figure 4-1: Straps Capture
20
Figure 4-2: Type II Straps Capture Timing
20
Figure 4-3: Type I Straps Capture Timing
21
Table 4-1: Standard Straps
21
Table 4-2: Debug Straps
22
Table 4-3: Additional Straps
23
5 Integrated Resistor and External Pull-Up/Pull-Down Resistor Requirements
24
Table 5-1: External Resistor Requirements and Integrated Pull-Up/Down
24
6 SP5100 Ballout Map
31
Figure 6-1: SP5100 Ball-Out Assignment (Left)
31
Figure 6-2: SP5100 Ball-Out Assignment (Right)
32
7 Signal Description
33
CPU Interface
33
LPC Interface
33
A-Link Express II Interface
34
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge)
34
USB Interface
35
Pata 66/100/133
35
Serial ATA Interface
36
HD Audio Interface
37
Real Time Clock Interface
37
Hardware Monitor
37
SPI ROM Interface
38
Northbridge / Power Management Interface
38
Smbus Interface / General Purpose Open Collector
40
External Event / General Event / General Power Management / General Purpose Open Collector
41
General Purpose I/O
43
Integrated Micro-Controller (IMC)
46
Reset / Clocks / ATE
47
Intruder Alert
49
Power and Ground
49
8 Functional Description
51
EHCI USB 2.0 and OHCI USB 1.1 Controllers
51
Figure 8-1: SP5100 USB 2.0 System Block Diagram
51
Table 8-1: EHCI Support for Power Management States
52
Table 8-2: EHCI Power State Summary
52
USB Power Management
52
SMI#/SCI Generation
53
Table 8-3: Causes of SMI# and SCI
53
LPC ISA Bridge
54
LPC Interface Overview
54
Figure 8-2: a Typical LPC Bus System
54
AMD SP5100 Databook 44409 Rev. 1.70 October
54
Table 8-4: LPC Cycle List and Data Direction
55
LPC Module Block Diagram
56
Integrated Micro-Controller (IMC)
56
Real Time Clock
56
Figure 8-3: Block Diagram of LPC Module
56
Functional Blocks of RTC
57
PATA Controller
57
SATA (Serial ATA) Controller
57
Figure 8-4: Block Diagram of Internal RTC
57
PCI Bridge
58
Figure 8-5: Block Diagram for the SATA Module
58
High Definition Audio
59
HD Audio Codec Connections
59
Power Management/Acpi
59
General Events and Gpios
59
Figure 8-6: HD Audio Codec Connections
59
Hardware Monitor Interface
60
Table 8-5: SMI, SCI, and Wake Event Support by GPIO and General Event Pins
60
Table 8-6: Functionality of the General Events and Gpios Across ACPI States
60
9 System Clock Specifications
62
System Clock Descriptions and Frequency Specifications
62
System Clock AC Specifications
62
Table 9-1: SP5100 System Clock Descriptions
62
Table 9-2: SP5100 System Clock Input Frequency Specifications
62
Table 9-3: SP5100 System Clock Output Frequency Specifications
62
Figure 9-1: Timing Labels for AC Specifications of the SP5100 Clocks
63
Figure 9-2: Timing Labels for AC Specifications of the SP5100 Diff Clocks
63
Figure 9-3: SP5100 Diff Clocks Rise and Fall Time Measurement
63
Table 9-4: 48Mhz USB Clock AC Specifications
63
Table 9-5: RTC X1 Clock AC Specifications
64
Table 9-6: LPC Clock AC Specifications
64
Table 9-7: PCI Clock AC Specifications
64
Table 9-8: PCI Express
65
Clock AC Specifications
65
Table 9-9: RTC 32-Khz Output Clock AC Specifications
65
10 States of Power Rails During ACPI S1 to S5 States
66
Table 10-1: State of each Power Rail During ACPI S1 to S5 States
66
11 Electrical Characteristics
67
Absolute Maximum Ratings
67
Functional Operating Range for Signal Input
67
Table 11-1: Absolute Maximum Rating
67
DC Characteristics
68
Table 11-2: DC Characteristics for Power Supplies to the SP5100
68
Table 11-3: DC Characteristics for Interfaces on the SP5100
68
Table 11-4: GPIO/GEVENT Input DC Characteristics
69
Table 11-5: GPIO/GEVENT Output DC Characteristics
72
Table 11-6: RTC Clock Output DC Characteristics
72
Reset Signal Requirements
73
RTC Battery Current Consumption
73
Table 11-7: Reset Signal Requirements
73
Table 11-8: RTC Battery Current Consumption
73
12 Package Information
74
Physical Dimensions
74
Figure 12-1: SP5100 21 MM X 21 MM 0.8 MM Pitch 528-FCBGA Package Outline
74
Table 12-1: SP5100 21 MM X 21 MM 0.8 MM Pitch 528-FCBGA Physical Dimensions
74
Pressure Specification
75
13 Thermal Information
76
Table 13-1 SP5100 Thermal Limits
76
14 Testability
77
Test Control Signals
77
Table 14-1: Signals for the Test Controller of the SP5100
77
Table 14-2: Test Mode Signals
77
Table 14-3: TEST0 Bit Sequence
77
XOR Chain Test Mode
78
Brief Description of an XOR Chain
78
Figure 14-1: Test Mode Capturing Sequence Timing
78
Figure 14-2: a Generic XOR Chain
78
Description of the SP5100 XOR Chain
79
Figure 14-3: On-Chip XOR Chain Connectivity
79
Table 14-4: Truth Table for an XOR Chain
79
Table 14-5: List of Pins on the SP5100 XOR Chain and the Order of Connection
79
Table 14-6: Pins Excluded from the XOR Chain
83
Appendix A: Pin Listing
84
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