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Clock Generator Registers
Field Name
VOL_DROP_DELAY
Static screen mode voltage control
Field Name
CG_TC_TMS
CG_TC_TDI
CG_TC_MODE
CG_TC_TDO_MASK
CG Interface to the Test Controller (TC) using IEEE JTAG protocol. This register can be written with 8 consecutive values for the inputs to the TC's
JTAG port. These 8 inputs are sent at consecutive TCK clock edges. The final value is held for indefinitely many TCK clock edges until the next
write to this register. The register can be used to walk through several states of the JTAG state machine and typically the state machine would be
left in a 'paused' state. The TDO values sampled at the 8 edges for which input was provided is available for readback from the TC_CG_TDO field
of the CG_TC_JTAG_1 register.
Field Name
TC_CG_TDO
TC_CG_DONE
TDO readback and status bits for the CG JTAG interface described in more detail in the CG_TC_JTAG_0 register description.
M56 Register Reference Manual
2-164
Bits
Default
31:0
0x100
delay (in sclk cycle) between static screen condition get detected till
voltage get dropped
CG_TC_JTAG_0 - RW - 32 bits - CLKIND:0x38
Bits
Default
7:0
0x0
8 consecutive values for TMS. Bit 0 is sent first.
15:8
0x0
8 consecutive values for TDI. Bit 0 is sent first.
17:16
0x0
Indicates what clock should be used for TCK in the JTAG transac-
tions.
31:24
0x0
A mask indicating whether the TDO value should be read back for a
given JTAG cycle. Bit 0 corresponds to the first TDO sample. This
mask can be used to prevent the readback of unknown values across
the bus interface during simulation. This field can be set to all 1's on
real hardware.
CG_TC_JTAG_1 - R - 32 bits - CLKIND:0x39
Bits
Default
7:0
0x0
8 consecutive sampled values of TDO. Bit 0 corresponds to the cycle
that the first bit of CG_TC_JTAG_0.CG_TC_TMS and
CG_TC_JTAG_0.CG_TC_TDI were sampled by the Test Controller.
31
0x0
Indicates whether the JTAG sequence has completed.
to CG_TC_JTAG_0
CG_TC_JTAG_0
Description
Description
0=No Clock
1=PCIE Reference Clock / 4
2=PCIE Reference Clock / 10
3=PCIE Reference Clock / 20
Description
0=We have completed less than 8 JTAG cycles since the last write
1=All 8 JTAG cycles have been completed since the last write to
© 2007 Advanced Micro Devices, Inc.
Proprietary
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