Clock Generator Registers - AMD M56 Reference Manual

2.5

Clock Generator Registers

Field Name
PLL_ADDR
PLL_WR_EN
PPLL_DIV_SEL
Clock generation block register index control
Field Name
PLL_DATA
Clock generation block register data
Field Name
SPLL_RESET
SPLL_SLEEP
SPLL_REF_DIV
SPLL_FB_DIV
SPLL_PULSEEN
SPLL_PULSENUM
SPLL_SW_HILEN
SPLL_SW_LOLEN
SPLL_DIVEN
SPLL_BYPASS_EN
SPLL_CHG_STATUS (R)
SPLL_CTLREQ
SPLL_CTLACK (R)
SPLL control register
© 2007 Advanced Micro Devices, Inc.
Proprietary
CLOCK_CNTL_INDEX - RW - 32 bits - CGDEC:0xE008
Bits Default
5:0 0x0
7 0x0
9:8 0x0
CLOCK_CNTL_DATA - RW - 32 bits - CGDEC:0xE00C
Bits Default
31:0 0x0
SPLL_FUNC_CNTL - RW - 32 bits - CLKIND:0x0
Bits Default
0 0x1
1 0x0
4:2 0x1
12:5 0x47
13 0x0
15:14 0x0
19:16 0x0
23:20 0x0
24 0x1
25 0x1
29 0x0
30 0x0
31 0x0
Description
Register address
0=Disable writes to CLOCK_CNTL_DATA
1=Enable writing to CLOCK_CNTL_DATA
0=PPLL_DIV0
1=PPLL_DIV1
2=PPLL_DIV2
3=PPLL_DIV3
Description
Register value
Description
0=Run
1=Reset
0=Power Up
1=Power Down
SPLL reference divider value
SPLL feedback divider value
0=Don't pulse clock
1=Send the number of pulses indicated by PULSENUM
Number of pulses required by SPLL
Post divider value for SPLL (high pulse section)
Post divider value for SPLL (low pulse section)
1=Enable PLL CLKOUT divider
1=Enable Bypass Clockout
1=Previous write/change to SPLL_FUNC_CNTL register has been
completed. SW should not issue another write to this register until
this bit is asserted
1=For debug purpose: when SW_DIR_CONTROL is set, assert this
bit will trigger an update of the PLL clock output mux control. Before
write to this bit, HILEN/LOLEN/PULSEEN/PULSENUM should
already contain the new set of value
1=For debug purpose: when SW_DIR_CONTROL is set, this value
replicates the value of the CTLREQ once the command has been
received and it is safe to send another request
M56 Register Reference Manual
Clock Generator Registers
2-155