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AMD SP5100
Databook
Technical Reference Manual
Rev. 1.70
P/N: 44409_sp5100_ds_pub
© 2010 Advanced Micro Devices, Inc.

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Summary of Contents for AMD SP5100

  • Page 1 AMD SP5100 Databook Technical Reference Manual Rev. 1.70 P/N: 44409_sp5100_ds_pub © 2010 Advanced Micro Devices, Inc.
  • Page 2 AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur.

  • Page 3: Revision History

    SBPWRGD; corrected condition for GPIO/IMC_GPIO and IDE pins’ VOH to IOH=-8.0mA. • Updated Table 14-5, “List of Pins on the SP5100 XOR Chain and the Order of Connection”: Corrected pin names at XOR# 113 and 114 to USB_FSD13P and USB_FSD12P.

  • Page 4: Table Of Contents

    Features of the SP5100 ......................8 Part Number and Branding ...................... 11 SP5100 Block Diagram ..................13 SP5100 Power on Sequence and Timing............. 14 Power Up and Down Sequences ..................... 14 SP5100 Strap Information ..................20 Integrated Resistor and External Pull-up/Pull-down Resistor Requirements .. 24 SP5100 Ballout Map ....................
  • Page 5 14.1 Test Control Signals ........................ 77 14.2 XOR Chain Test Mode ......................78 14.2.1 Brief Description of an XOR Chain ....................78 14.2.2 Description of the SP5100 XOR Chain .................... 79 Appendix A: Pin Listing ....................84 Table of Contents...
  • Page 6 Figure 1-1: SP5100 Rev A14 Branding Diagram ....................11 Figure 1-2: SP5100 Rev A15 Branding Diagrams....................12 Figure 2-1: SP5100 Block Diagram Showing the Internal PCI Devices and Major Function Blocks ......13 Figure 3-1: SP5100 Power Up/Down Sequence ..................... 15 Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence ...................
  • Page 7 Table 14-3: TEST0 Bit Sequence .......................... 77 Table 14-4: Truth Table for an XOR Chain ......................79 Table 14-5: List of Pins on the SP5100 XOR Chain and the Order of Connection ............ 79 Table 14-6: Pins Excluded from the XOR Chain ..................... 83...

  • Page 8: Introduction

    44409 Rev. 1.70 Oct 10 1 Introduction AMD’s SP5100 is a Southbridge that integrates key I/O, communications, and other features required in a state-of-the-art server platform into a single device. It is specifically designed to operate with AMD’s server Northbridges.
  • Page 9 RAID 10 (requires use of 4 or more SATA 256-byte battery-backed CMOS RAM ports) functionalities across all 6 ports.  Hardware supported century rollover Note: AMD does not provide RAID drivers  for the SP5100. RTC battery monitoring feature AHCI Support Power Management ...
  • Page 10 AMD SP5100 Databook 44409 Rev. 1.70 October 10  DIPM on SATA Note: Advanced Power Management (APM) is not supported. Hardware Monitor  Hardware monitoring support for voltage sensors, fan control, and digital TSI to AM3 processors. Note: Temperature monitoring is NOT supported.

  • Page 11: Part Number And Branding

    Note 5 Note 6 218-0660013 Note 7 Figure 1-1: SP5100 Rev A14 Branding Diagram Note 1: Marketing logo Note 2: AMD product type Note 3: Date Code (YYWW). YY-assembly start year, WW-assembly start week. Note 4: COO. Country of origin (assembly site) Note 5: This is wafer foundry’s lot number for the product.

  • Page 12: Figure 1-2: Sp5100 Rev A15 Branding Diagrams

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 SP5100 Rev A15 Eutectic Part Production Branding SP5100 Rev A15 Lead Free Part Production Branding Note 1 SOUTHBRIDGE Note 2 SOUTHBRIDGE YYWW Note 3 YYWW Note 4 WXXXXX Note 5 WXXXXX Note 6...

  • Page 13: Sp5100 Block Diagram

    25MHz X1 / X2 8250 TIMER SPEAKER ACPI / HW SMBUS Monitor SMBUS PWRGOOD GEVENT[7:0],SLPBUTTON LDTRST# GPM [9:0]TEMPDEAD, RESET# TEMPCAUT, SHUTDOWN,DC_STOP# SCIOUT, SOFF# Figure 2-1: SP5100 Block Diagram Showing the Internal PCI Devices and Major Function Blocks SP5100 Block Diagram...

  • Page 14: Sp5100 Power On Sequence And Timing

    Figure 3-2 below. A power detection circuit is integrated into the SP5100. This circuit will monitor SB PWR_GOOD and will assert A_RST# and LDT_RST# for as long as SB PWR_GOOD is false. After SB PWR_GOOD has been asserted, A_RST#, followed by LDT_RST#, will be de-asserted.

  • Page 15: Figure 3-1: Sp5100 Power Up/Down Sequence

    ( See Note 5) KBRST# ( See Note 4) PCIRST # LDT_ RST# PCIE_ RCLKP /N PCICLK [5:0] ( Note 8) ALLOW _ LDTSTP Note 11 LDT_ STP# Figure 3-1: SP5100 Power Up/Down Sequence SP5100 Power on Sequence and Timing...

  • Page 16: Figure 3-2: Sp5100 S3/S0 Power Up/Down Sequence

    (See Note 1 & 2) System clocks T13A SB PWRGOOD NB_PWRGD LDT_PG A_RST# (See Note 5) KBRST# (See Note 4) PCIRST# LDT_RST# PCIE_RCLKP/N PCICLK[5:0] ALLOW_LDTSTP (Note 8) LDT_STP# Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence SP5100 Power on Sequence and Timing...

  • Page 17: Figure 3-3: Circuit For Maintaining Proper Relationship Between +V5_Vref And Vddq

    PCIE_VDDR, CKVDD_1.2V +1.8 V Note 2: V5_VREF is used in the SP5100 for the 5-V PCI signal tolerance. VDDQ (+3.3 V) & VDD33_18 (3.3 V) must not exceed V5_VREF by more than 0.6 V at any time during ramp up, steady state, or ramp down.

  • Page 18: Figure 3-4: Timing For Sb Pwr_Good De-Asserted To Rsmrst# De-Asserted

    CPU_VDDIO power. On subsequent power up, S5  S0, the timing on T9B will apply. CPU_VDDIO LDT_STP# Timing is system depended SB PWRGOOD Figure 3-5: Timing for LDT_STP# assertion on first power up (G3  S5) SP5100 Power on Sequence and Timing...

  • Page 19: Figure 3-6: S5_3.3V Power Down Sequence Requirement

    AMD SP5100 Databook Note 12: The S5_3.3V ramp down should be controlled to achieve a slew rate of 8mV/ µS or lower. S5_3.3V Min Slew Rate: 8 mV/µS Figure 3-6: S5_3.3V Power Down Sequence Requirement SP5100 Power on Sequence and Timing...

  • Page 20: Sp5100 Strap Information

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 4 SP5100 Strap Information There are two kinds of strap-latching logic, Type I and Type II. Type I straps will be latched on G3 to S5 transition on rising edge of RSMRST#. Type II straps are latched on S5 to S0 transition after rising edge of PWR_GOOD assertion.

  • Page 21: Figure 4-3: Type I Straps Capture Timing

    44409 Rev. 1.70 October 10 AMD SP5100 Databook S5 3.3V /S5 1.2V RSM_RST# System dependent (10 ms or greater) 31 ms 2RTC 25 ms RTC_CLK 25 ms Strap signal is tristate can be High Strap signal must be Strap signal is tristate...

  • Page 22: Table 4-2: Debug Straps

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 Pad Name Strap Name Type Description Integrated Microcontroller (IMC) IMC_ENABLE 0 V – Disable IMC 3.3 V – Enable IMC Revision A11 strap defination LPCCLK0 Booting from PCI memory 0 V – disable PCI ROM boot (Default) 3.3 V –...

  • Page 23: Table 4-3: Additional Straps

    44409 Rev. 1.70 October 10 AMD SP5100 Databook Pad Name Strap Name Type Description Bypass PCI PLL 0 V – Bypass internal PLL clock . Use REQ3# as A-Link bypass clock PCI_AD27 PCI_PLL Use GNT3# as B-Link bypass clock 3.3 V – Use internal PLL-generated PLL CLK (Default) (Internal PU of 15 kΩ)

  • Page 24: Integrated Resistor And External Pull-Up/Pull-Down Resistor Requirements

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 5 Integrated Resistor and External Pull-up/Pull-down Resistor Requirements Table 5-1: External Resistor Requirements and Integrated Pull-Up/Down Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD IDE_DRQ Integrated 5.6 K...
  • Page 25 44409 Rev. 1.70 October 10 AMD SP5100 Databook Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD AD[31:23] Integrated 15 K Pull-up PM_REG 41h / PM_REG 40h Default: Pull-up enabled FRAME# Integrated 8.2 K Pull-up —...
  • Page 26 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD Power SLP_S2/ Integrated 10 K Pull-down PM2_Rg F8h Manage- GPM9# Default: Pull-down ment enabled PWR_BTN#...
  • Page 27 44409 Rev. 1.70 October 10 AMD SP5100 Databook Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD USB_OC3#/GPM3# Integrated 10 K Pull-up PM2_Rg F6h Default: Pull-up enabled USB_OC4#/GPM4# Integrated 10 K Pull-up...
  • Page 28 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD SPI_DO/GPIO11 Integrated 10 K Pull down PM2_Rg E2h Default: Pull-down Enabled SPI_DI/GPIO12 Integrated 10 K...
  • Page 29 44409 Rev. 1.70 October 10 AMD SP5100 Databook Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD Integrated 27 Ω IDE_D13/FC_ADQ13/GPIO28 Series PM2_Rg E7h Default: Pull-up/Pull- down not enabled Integrated 27 Ω...
  • Page 30 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Value of Register for Interface Signal Name Integrated / External Resistor Type programming the Resistor integrated PU/PD BMREQ#/REQ5#/GPIO65 Integrated 8.2 K See Note PM2_Rg F0h Default: Pull-up/Pull- down not enabled LLB#/GPIO66 Integrated 10 K...

  • Page 31: Sp5100 Ballout Map

    INTF#/GPIO34 GNT3#/GPIO72 SATA_RX0P SATA_TX2N BMREQ#/REQ5 AVSS_SATA_1 AD31 GNT0# INTE#/GPIO33 REQ1# GNT2# CLKRUN# SATA_TX0P SATA_TX1N SATA_RX1N SATA_RX2P SATA_TX3P #/GPIO65 AVSS_SATA_2 VSS_49 INTG#/GPIO35 INTH#/GPIO36 GNT1# GNT4#/GPIO73 REQ3#/GPIO70 V5_VREF SATA_TX0N SATA_TX1P SATA_RX1P SATA_RX2N SATA_TX3N Figure 6-1: SP5100 Ball-out Assignment (Left) SP5100 Ballout Map...

  • Page 32: Figure 6-2: Sp5100 Ball-Out Assignment (Right)

    AVDD_SATA_5 IDE_D9/GPIO24 IDE_D3/GPIO18 IDE_D15/GPIO30 IDE_IOW# IDE_IOR# CLK_REQ3#/SAT SATA_TX4N SATA_RX4N SATA_RX5P AVDD_SATA_6 IDE_D7/GPIO22 IDE_D10/GPIO25 IDE_D4/GPIO19 IDE_D13/GPIO28 IDE_D1/GPIO16 IDE_D0/GPIO15 IDE_DRQ A_IS1#/GPIO6 SATA_IS0#/GPIO SATA_TX4P SATA_RX4P SATA_RX5N AVDD_SATA_7 IDE_D8/GPIO23 IDE_D5/GPIO20 IDE_D11/GPIO26 IDE_D2/GPIO17 IDE_D14/GPIO29 VSS_50 VDD33_18_4 Figure 6-2: SP5100 Ball-out Assignment (Right) SP5100 Ballout Map...

  • Page 33: Signal Description

    S5_3.3 V Encoded DMA/Bus Master Request 0 LDRQ1#/GNT5#/ Encoded DMA/Bus Master Request 1 / PCI bus Grant 5 3.3 V GPIO68 from SP5100 / GPIO 68 LPC_SMI#/EXTEVNT1# S5_3.3 V LPC SMI / External Event 1 SERIRQ 3.3 V Serial IRQ...

  • Page 34: A-Link Express Ii Interface

    3.3 V (5-V Tolerance) agent that access to the bus has been granted. GNT3#/GPIO72 3.3 V (5-V Tolerance) PCI Bus Grant 3 from SP5100 / GPIO 72 GNT4#/GPIO73 3.3 V (5-V Tolerance) PCI Bus Grant 4 from SP5100 / GPIO 73 INT[H:E]#/GPIO[36:33] 3.3 V (5-V Tolerance) PCI Interrupt [H:E] / GPIO [36:33]...

  • Page 35: Usb Interface

    PATA 66/100/133 Note: The SP5100 does not support the flash controller function. The flash controller should be disabled by BIOS, and the interface can only be used for IDE function (or as GPIOs, in case of the IDE data bus bits).

  • Page 36: Serial Ata Interface

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 Pin Name Type Voltage Functional Description IDE_IORDY/FC_FBCKIN 3.3 V (5-V Tolerance) IDE IO Ready IDE_IRQ/FC_INT2 3.3 V (5-V Tolerance) IDE Interrupt Request/ IDE_A0/FC_OE# 3.3 V (5-V Tolerance) IDE Address bus bit 0 IDE_A1/FC_FBCLKOUT 3.3 V (5-V Tolerance)

  • Page 37: Hd Audio Interface

    SATA interlock switches, it should connect the statuses of the switches to those pins. The SP5100 will sense the statuses of those pins and can generate a PME or interrupt when the statuses change. Normally, an inter-lock switch is required for supporting hot plug.

  • Page 38: Spi Rom Interface

    Hardware Monitor Analog PWR AVSS Analog Ground Hardware Monitor Analog GND *Note: Temperature monitoring function is NOT supported on the SP5100. TEMPIN[3:0] can only be used as GPIOs. 7.11 SPI ROM Interface SPI ROM is supported up to 33 MHz. Maximum ROM size supported is 16 MB. Burst read and fast read cycles are not supported.
  • Page 39 SMBus Alert / Thermal Trip / General Event 2 THRMTRIP#/ GEVENT2# Thermal Trip: Signal indicates to the SP5100 that a thermal trip has occurred. Its assertion will cause the SP5100 to transition the system to S5 immediately, without waiting for the STPGNT message from the processor.

  • Page 40: Smbus Interface / General Purpose Open Collector

    Voltage Functional Description S3_STATE/ S5_3.3V S3 State: Assertion of S3_STATE by the SP5100 indicates to the GEVENT5# power supply that the system has transitioned into S3 state. Asserted after the Sleep S3 command is completed. De-assertion indicates that the system is leaving S3 state. De-assertion takes place after SUS_STAT# is de-asserted.

  • Page 41: External Event / General Event / General Power Management / General Purpose Open Collector

    EXTEVENT/GEVENT/GPM/ GPOC pins for the desired functions, see the AMD SP5100 Register Reference Guide. The table below lists all the EXTEVENT/GEVENT/GPM/GPOC pins on the SP5100. The Default Type column shows the state of the pin (default function) after de-assertion of the PCI host bus reset (A_RST#), which happens after power up or after system reset.
  • Page 42 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Default Internal Ball Name Type Resistor Voltage and Type Functional Description (Default Function (Default Domain (Default in Blue) State in Blue) Blue) USB_OC3#/ USB Over Current 3/ 10-kΩ PU IR_RX1/ 3.3V_S5 Input Infrared Receive 1/ 10-kΩ...

  • Page 43: General Purpose I/O

    GPIO pins for the desired functions, see the AMD SP5100 Register Reference Guide. The table below lists all the GPIO pins on the SP5100. The Default Type column shows the state of the pin (default function) after de-assertion of the PCI host bus reset (A_RST#), which happens after power up or after system reset.
  • Page 44 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Default Internal Ball Name Type Resistor Voltage and Type Functional Description (Default Function (Default Domain (Default in Blue) State in Blue) Blue) IDE_D[15:8]/ 3.3V_S0 Output IDE data [15:8]/ 27-Ω series GPIO[30:23] (5-V Tolerance)
  • Page 45 44409 Rev. 1.70 October 10 AMD SP5100 Databook Default Internal Ball Name Type Resistor Voltage and Type Functional Description (Default Function (Default Domain (Default in Blue) State in Blue) Blue) 10-kΩ PU VIN0/ Voltage Input 0/ 3.3V_S5 Input 10-kΩ PD...

  • Page 46: Integrated Micro-Controller (Imc)

    10-kΩ PD (IMC) GPIO [41:18] Notes: For information on how to configure the GPIO pins, see the AMD SP5100 Register Reference Guide. Notice that the IMC GPIOs can also be used as general purpose GPIOs. * The “default function” and the “default state” refer to function and state of the pin after deassertion of PCI host bus reset (A_RST#), i.e., right after system power up or reset.

  • Page 47: Reset / Clocks / Ate

    (5-V Tolerance) IMC_GPIO[41:18] S5_3.3V IMC GPIO [41:18] *Note: The IMC power management controller is NOT supported by the SP5100. The pins can only be used as GPIOs. 7.17 Reset / Clocks / ATE Note: Clock generator function is NOT SUPPORTED by the SP5100.
  • Page 48 14M_25M_48M_OSC RSMRST# S5_3.3V Resume Reset from Motherboard – Assertion of RSMRST# resets all SP5100 registers to their default values. It also causes all reset signals originating from the SP5100 (A_RST#, PCIRST#, LDT_RST#, AZ_RST#, AC_RST#) to be issued. RSRMT# should be asserted when system power is being applied.

  • Page 49: Intruder Alert

    44409 Rev. 1.70 October 10 AMD SP5100 Databook Pin Name Type Voltage Functional Description TEST0 S5_3.3V ATE Test 0 TEST1 S5_3.3V ATE Test 1 TEST2 S5_3.3V ATE Test 2 7.18 Intruder Alert Pin Name Type Voltage Functional Description Intruder_Alert# VBAT Intruder alert sense input 7.19...
  • Page 50 AMD SP5100 Databook 44409 Rev. 1.70 October 10 Voltage/ ACPI Signal Name GND reference Note Description Ground STATE AVSS_SATA[20:1] SATA Analog Ground (Plane) AVSS Analog Ground for Hardware Monitor. AVSSC Analog Ground for USB PHY PLL. AVSS_USB_[24:1] GND_USB Analog Ground for USB PHY Note 1: These power rails should be filtered.

  • Page 51: Functional Description

    Port 0/1/2 Controller Controls Port OHCI1 (dev-18) Port 3/4/5 OHCI (dev-20) Port 12/13 EHCI (dev-18) Port 0-5 OHCI0 (dev-19) Port 6/7/8 OHCI1 (dev-19) Port 9/10/11 EHCI (dev-19) Port 6 - 11 Figure 8-1: SP5100 USB 2.0 System Block Diagram Functional Description...

  • Page 52: Usb Power Management

    Fully awake backward compatible state. All logic in full power mode. Optional Not supported in SP5100. USB Sleep state with EHCI bus master capabilities disabled. All USB ports in suspended state. All logic in low latency power saving mode because of low latency returning to D0 state.

  • Page 53: Smi#/Sci Generation

    Certain system events are routable between SMI# and SCI. When an event is routed to SMI#, an SMI# assertion message will be sent by the SP5100 to the processor and it will enter SMM space. The SMI status remains active until the EOS bit is set. When the EOS is set, SMI# de-assertion message will be sent to the processor for at least 4 PCICLK cycles.

  • Page 54: Lpc Isa Bridge

    A typical setup of the system with LPC interface is shown in Figure 8-2 below. Here the ISA bus is internal to SP5100 and is used for connecting to the legacy DMA logic. The LPC controller connects to the A-Link bus on one side and the LPC and SPI bus on the other side.

  • Page 55: Table 8-4: Lpc Cycle List And Data Direction

    44409 Rev. 1.70 October 10 AMD SP5100 Databook read/write. It supports up to two bus masters and 7 DMA channels. A bus master or DMA agent uses LDRQ pin to assert bus master or DMA request. The host controller uses LFRAME# to indicate the start or termination of a cycle.

  • Page 56: Lpc Module Block Diagram

    The Real Time Clock (RTC) is used for updating a computer’s time. In addition to that, it also generates interrupts for periodic events and pre-set alarm. The SP5100’s RTC includes a 256-byte CMOS RAM, which is used to store the configuration of a computer, such as the number and type of floppy drive, graphics adapter, base memory, checksum value, etc.

  • Page 57: Functional Blocks Of Rtc

    44409 Rev. 1.70 October 10 AMD SP5100 Databook 8.5.1 Functional Blocks of RTC The internal RTC is made of two parts: one is an analog circuit, powered by a battery VBAT, and the other part is a digital circuit, powered by a main power VDD.

  • Page 58: Pci Bridge

    Figure 8-5: Block Diagram for the SATA Module PCI Bridge SP5100 PCI Bridge supports 5 PCI slots by default but can be optionally configured to support a 6 slot. The PCI bridge runs at 33 MHz and can support CLKRUN# function with individual clock override (option not to stop specific PCICLK).

  • Page 59: High Definition Audio

    44409 Rev. 1.70 October 10 AMD SP5100 Databook SP5100 has a strapping option for loading the boot codes from the PCI bus on the very first boot (1 boot after RSMRST#). Subsequent boots will revert back to the ROM selection determined by the ROM straps or PMIO programming.

  • Page 60: Hardware Monitor Interface

    § If IMC is disabled, the IMC GPIOs maintain state in S4 and S5 only if the register field PMIO_BB[5] is set to 1. See the AMD SP5100 Register Reference Guide for a more detailed description of the register. 8.12 Hardware Monitor Interface The hardware monitor interface supports voltage sensors, fan control, and digital TSI to AM3 processors.
  • Page 61 44409 Rev. 1.70 October 10 AMD SP5100 Databook Pin Name Type Voltage Functional Description 3.3V(5V FANIN2/GPIO52 Fan Tachometer Input 2 / GPIO 52 Tolerance) ® CLK_REQ1#/SATA_IS4/ PCI Express Clock Request / SATA Interlock 3.3V FANOUT3/GPIO39 Switch Port 4 (input) / Fan Output 3 / GPIO39...

  • Page 62: System Clock Specifications

    32.768 KHz System Clock AC Specifications Table 9-4 to Table 9-9 list all the AC specifications of SP5100 clocks, some at specific VIH/VIL combinations. Figure 9-1 to Figure 9-3 below illustrate the timing labels that appear in those tables. System Clock Specifications...

  • Page 63: Figure 9-1: Timing Labels For Ac Specifications Of The Sp5100 Clocks

    T 62 Vcross max Vcross min T 64 T 65 Figure 9-2: Timing Labels for AC Specifications of the SP5100 Diff Clocks FALL RISE PCIE_CLKP +PCIE_CLKN Figure 9-3: SP5100 Diff Clocks Rise and Fall Time Measurement Table 9-4: 48MHz USB Clock AC Specifications...

  • Page 64: Table 9-5: Rtc X1 Clock Ac Specifications

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 48 MHz USB Symbol Parameter Units Note Max Jitter Duty Cycle Notes: 1 Clock frequency tolerance is +/- 100 ppm 2 VIL= 0.4 V ; VILmax = 0.6 V and VILmin = 0 V VIH = 2.4 V;...

  • Page 65: Table 9-8: Pci Express

    44409 Rev. 1.70 October 10 AMD SP5100 Databook ® Table 9-8: PCI Express Clock AC Specifications Symbol Parameter Units Note Clock Period 9.872 10.128 SSC disabled Clock rise edge rate V/ns See Figure 9-2 and Note below Clock fall edge rate...

  • Page 66: States Of Power Rails During Acpi S1 To S5 States

    44409 Rev. 1.70 October 10 10 States of Power Rails during ACPI S1 to S5 States SP5100 supports the ACPI states S1 to S5. Table 10-1 below shows the expected state of each power rail during these power states. Table 10-1: State of Each Power Rail during ACPI S1 to S5 States...

  • Page 67: Electrical Characteristics

    See Section 3 for signal names Any 3,.3 / 5 V tolerant -0.5 to VREF+0.5 input signal 11.2 Functional Operating Range for Signal Input The functional operating range for any signal input to the SP5100 is +/-5% of the signal's typical input level. Electrical Characteristics...

  • Page 68: Dc Characteristics

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 11.3 DC Characteristics Table 11-2: DC Characteristics for Power Supplies to the SP5100 Typical Signal Name Description Min. Voltage Max. Voltage Unit Voltage AVDDCK_1.2V Core PLL digital power 1.14 1.26 A-Link Express II PLL PCIE_PVDD 1.14...

  • Page 69: Table 11-4: Gpio/Gevent Input Dc Characteristics

    Output High Voltage / VCPU_IO Internal Pull-up Voltage Input Leakage Current +/-10 µA Input Capacitance All signals from SP5100 to CPU are open drain NB – ALLOW_LDTSTP Input Low Voltage -0.5 Input High Voltage Output Low Voltage IOL = 4.0 mA...
  • Page 70 AMD SP5100 Databook 44409 Rev. 1.70 October 10 ViL(V) ViH (V) Pin Name Voltage 3.3 V SPKR/GPIO2 -0.5 0.3* VDDQ 0.7*VDDQ V5_Ref + 0.25 (5-V Tolerance) 3.3 V FANOUT0/GPIO3 -0.5 0.3* VDDQ 0.7*VDDQ V5_Ref + 0.25 (5-V Tolerance) SMARTVOLT1/ 3.3 V -0.5...
  • Page 71 44409 Rev. 1.70 October 10 AMD SP5100 Databook ViL(V) ViH (V) Pin Name Voltage FANIN2/GPIO52 3.3 V -0.5 0.3* VDDQ 0.7*VDDQ V5_Ref + 0.25 0.7* VIN[7:0]/GPIO[60:53] 3.3 V -0.5 0.3* S5_3.3V S5_3.3V + 0.25 S5_3.3V 0.7* TEMPIN[2:0]/GPIO[63:61] 3.3 V -0.5 0.3* S5_3.3V...

  • Page 72: Table 11-5: Gpio/Gevent Output Dc Characteristics

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 ViL(V) ViH (V) Pin Name Voltage 3.3 V SDA0/GPOC1# -0.5 0.3* VDDQ 0.7*VDDQ V5_Ref + 0.25 (5-V Tolerance) 0.7* SCL1/GPOC2# S5_3.3V -0.5 0.3* S5_3.3V S5_3.3V + 0.25 S5_3.3V 0.7* SDA1/GPOC3# S5_3.3V -0.5 0.3* S5_3.3V...

  • Page 73: Reset Signal Requirements

    RTC are normally rated for 170 mAh and the worst case current consumption for the SP5100 is 4.0 µA. Thus, the life of battery will be calculated as follows: 170,000 µAh / 4 µA = 42,500 h = 4.8 years...

  • Page 74: Package Information

    44409 Rev. 1.70 October 10 12 Package Information 12.1 Physical Dimensions MOD-00067-RevA-p1 Figure 12-1: SP5100 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Package Outline Table 12-1: SP5100 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Physical Dimensions Ref. Min(mm) Nominal (mm) Max.

  • Page 75: Pressure Specification

    44409 Rev. 1.70 October 10 AMD SP5100 Databook 12.2 Pressure Specification To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below:  It is recommended that the maximum load that is evenly applied across the contact area between the thermal management device and the die does not exceed 6 lbf.

  • Page 76: Thermal Information

    The maximum ambient temperature is dependent on the heat sink's local ambient conditions as well as the chassis' external ambient, and the value given here is based on AMD’s reference server heat sink solution for the SP5100. Refer to Chapter 5 in the Thermal Design and Analysis Guidelines for SP5100 for heat sink and thermal design guidelines.

  • Page 77: Testability

    A high on TEST1 should be followed by a bit sequence on TEST0 to define the test mode into which the SP5100 will enter. A new test mode can be entered when a new bit sequence is transmitted. In addition to resetting the test controller asynchronously with TEST1, a bit sequence can also be used to synchronously change the test mode.

  • Page 78: Xor Chain Test Mode

    Note that once TEST1 is set to one, TEST0 needs to be asserted to one for at least 8 clocks before transmitting the test mode bit sequence. The rising of “Internal Test Mode” in the diagram indicates the time when the SP5100 enters into test mode. TEST1 TEST0 ( TEST0 = 1 ) >...

  • Page 79: Description Of The Sp5100 Xor Chain

    KBRST#/GEVENT1# chain and is the end of the chain. Table 14-5 lists all pads that are on the SP5100 XOR SERIRQ chain, as well as and their order of connection. Pads are chained together in the shown order, i.e., pad number 1 is the first pad on the XOR chain, pad number 2 the second, and so on.
  • Page 80 AMD SP5100 Databook 44409 Rev. 1.70 October 10 XOR # Pin Name XOR # Pin Name AD25 FANIN1/GPIO51 AD27 FANIN0/GPIO50 AD28 FANOUT0/GPIO3 FRAME# FANOUT2/GPIO49 IRDY# FANOUT1/GPIO48 AD24 AZ_SDOUT AD26 AZ_BITCLK AD19 AZ_SYNC AD16 A_RST# TRDY# AZ_SDIN3/GPIO46 AD21 PCIRST# AD22 AZ_RST#...
  • Page 81 44409 Rev. 1.70 October 10 AMD SP5100 Databook XOR # Pin Name XOR # Pin Name VIN7/GPIO60 IMC_GPIO28 VIN6/GPIO59 IMC_GPIO26 VIN5/GPIO58 IMC_GPIO24 TEMPIN3/TALERT#/GPIO64 IMC_GPIO23 TEMPIN2/GPIO63 IMC_GPIO22 TEMPIN1/GPIO62 IMC_GPIO21 TEMPIN0/GPIO61 IMC_GPIO20 USB_OC2#/GPM2# IMC_GPIO5 USB_OC3#/GPM3# IMC_GPIO6 IDE_RST#/F_RST#/ USB_OC4#/IR_RX/GPM4# IMC_GPO3 USB_OC5#/IR_TX/GPM5# ALLOW_LDTSTP USB_OC6#/IR_CTRL/...
  • Page 82 AMD SP5100 Databook 44409 Rev. 1.70 October 10 XOR # Pin Name XOR # Pin Name IDE_D1/GPIO16 IDE_D7/GPIO22 IDE_D0/GPIO15 SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/ IDE_DRQ GPIO6 IDE_D14/GPIO29 SCL0/GPOC0# IDE_D2/GPIO17 CLK_REQ0#/SATA_IS3#/ IDE_D13/GPIO28 GPIO0 IDE_D11/GPIO26 CLK_REQ1#/SATA_IS4#/ FANOUT3/GPIO39 IDE_D4/GPIO19 LAN_RST#/GPIO13 IDE_D9/GPIO24 SERIRQ IDE_D6/GPIO21 IDE_D5/GPIO20 IDE_D10/GPIO25 IDE_D8/GPIO23...

  • Page 83: Table 14-6: Pins Excluded From The Xor Chain

    44409 Rev. 1.70 October 10 AMD SP5100 Databook 14.2.2.1 Unused Pins The pins that are part of the XOR chain (see Table 14-5) but are not used for testing must be pulled-up or down before the XOR chain is activated. No pins in the XOR chain should be left floating. All digital or analog pins not included in Table 14-5 are not part of the XOR chain and can be left floating during an XOR test.

  • Page 84: Appendix A: Pin Listing

    AMD SP5100 Databook 44409 Rev. 1.70 October 10 Appendix A: Pin Listing Processor Interface PCICLK4 ALLOW_LDTSTP PCICLK5/GPIO41 LDT_PG A_RST# LDT_STP# PCIRST# LDT_RST# INTE#/GPIO33 PROCHOT# INTF#/GPIO34 LPC Interface INTG#/GPIO35 LPCCLK0 INTH#/GPIO36 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 LPC_SMI#/EXTEVNT1# AD10...
  • Page 85 44409 Rev. 1.70 October 10 AMD SP5100 Databook DEVSEL# USB_HSD1N IRDY# USB_HSD0P TRDY# USB_HSD0N USBCLK/14M_25M_48M_OSC STOP# USB_RCOMP PERR# ATA66/100/133 SERR# IDE_RST#/F_RST#/IMC_GPO3 LOCK# IDE_IORDY AA24 REQ0# IDE_IRQ AA25 REQ1# IDE_A0 REQ2# IDE_A1 AB23 REQ3#/GPIO70 IDE_A2 REQ4#/GPIO71 IDE_DACK# AB24 BMREQ#/REQ5#/GPIO65 IDE_DRQ AD25...
  • Page 86 AMD SP5100 Databook 44409 Rev. 1.70 October 10 SATA_TX3N AE13 NB_DISP_CLKN SATA_RX3N AB14 NB_HT_CLKP SATA_RX3P AC14 NB_HT_CLKN SATA_TX4P AE14 CPU_HT_CLKP SATA_TX4N AD14 CPU_HT_CLKN SATA_RX4N AD15 SLT_GFX_CLKP SATA_RX4P AE15 SLT_GFX_CLKN SATA_TX5P AB16 GPP_CLK0P SATA_TX5N AC16 GPP_CLK0N SATA_RX5N AE16 GPP_CLK1P SATA_RX5P AD16...
  • Page 87 44409 Rev. 1.70 October 10 AMD SP5100 Databook SPI_CS1#/GPIO32 IMC_GPIO35 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 NB / Power Mgmt IMC_GPIO37 SLP_S2/GPM9# IMC_GPIO38 SLP_S3# IMC_GPIO39 SLP_S5# IMC_GPIO40 PWR_BTN# IMC_GPIO41 PWR_GOOD General Events SUS_STAT# RI#/EXTEVNT0# TEST0 LPC_SMI#/EXTEVNT1# TEST1 GA20IN/GEVENT0# TEST2 KBRST#/GEVENT1# SMBALERT#/THRMTRIP#/ Integrated Micro-controller GEVENT2#...
  • Page 88 AMD SP5100 Databook 44409 Rev. 1.70 October 10 CLK_REQ3#/SATA_IS1#/ FANOUT2/GPIO49 AD18 GPIO6 FANIN0/GPIO50 FANIN1/GPIO51 NB_PWRGD FANIN2/GPIO52 VIN0/GPIO53 DDC1_SDA/GPIO8 VIN1/GPIO54 DDC1_SCL/GPIO9 AA20 VIN2/GPIO55 SATA_IS0#/GPIO10 AE18 VIN3/GPIO56 SPI_DO/GPIO11 VIN4/GPIO57 SPI_DI/GPIO12 VIN5/GPIO58 LAN_RST#/GPIO13 VIN6/GPIO59 ROM_RST#/GPIO14 VIN7/GPIO60 IDE_D0/GPIO15 AD24 TEMPIN0/GPIO61 IDE_D1/GPIO16 AD23 TEMPIN1/GPIO62 IDE_D2/GPIO17...
  • Page 89 44409 Rev. 1.70 October 10 AMD SP5100 Databook AVDDRX_0 PCIE_CK_VSS_13 AVDDRX_1 PCIE_CK_VSS_14 AVDDRX_2 PCIE_CK_VSS_15 AVDDRX_3 PCIE_CK_VSS_16 AVDDRX_4 PCIE_CK_VSS_17 AVDDRX_5 PCIE_CK_VSS_18 AVDDC PCIE_CK_VSS_19 AVSSC PCIE_CK_VSS_2 PCIE_CK_VSS_20 USB Analog Ground PCIE_CK_VSS_21 AVSS_USB_1 PCIE_CK_VSS_3 AVSS_USB_2 PCIE_CK_VSS_4 AVSS_USB_3 PCIE_CK_VSS_5 AVSS_USB_4 PCIE_CK_VSS_6 AVSS_USB_5 PCIE_CK_VSS_7 AVSS_USB_6...
  • Page 90 AMD SP5100 Databook 44409 Rev. 1.70 October 10 AVSS_SATA_20 VSS_5 VSS_6 Core Power VSS_7 VDD_1 VSS_8 VDD_2 VSS_9 VDD_3 VSS_10 VDD_4 VSS_11 VDD_5 VSS_12 VDD_6 VSS_13 VDD_7 VSS_14 VDD_8 VSS_15 VDD_9 VSS_16 3.3V I/O Power VSS_17 VDDQ_1 VSS_18 VDDQ_2 VSS_19...

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