Power Limit For The V; Package Power Limits For Multiple Turbo Modes; Cc Power Plane Write / Read; Power Limit Data For - Intel BX80619I73820 Design Manual

PECI Interface
7.1.4.4

Power Limit for the V

This feature allows the PECI host to program the power limit over a specified time or
control window for the V
(voltage regulator) capabilities. The units for the Power Limit and Control Time Window
are determined as per the Package Power SKU Unit settings described in
Section 7.1.2.7.2. The Power Limit Enable bit in
this feature. Setting the Clamp Mode bit allows the cores to go into power states below
what the operating system originally requested.
Figure 7-32. Power Limit Data for V
31 24
RESERVED
7.1.4.5

Package Power Limits For Multiple Turbo Modes

This feature allows the PECI host to program two power limit values to support multiple
turbo modes. The operating systems and drivers can balance the power budget using
these two limits. Two separate PECI requests are available to program the lower and
upper 32 bits of the power limit data shown in
Limit and Control Time Window are determined as per the Package Power SKU Unit
settings described in
go into power states below what the operating system originally requested. The Power
Limit Enable bit should be set to enable the power limiting function.
Figure 7-33. PKG_TURBO_POWER_LIMIT Data
63 56
RESERVED
31 24
RESERVED
Thermal/Mechanical Specifications and Design Guide
Power Plane Write / Read
CC
power plane. Actual values are chosen based on the VR
CC
Power Plane
CC
23 17 16
Control Time Clamp
Window Mode
VCC Power Plane Power Limit Data
Section 7.1.2.7.2. Setting the Clamp Mode bit allows the cores to
55 49 48
Control Time Clamp
Window #2 Mode #2
Package Power Limit 2
23 17 16
Control Time Clamp
Window #1 Mode #1
Package Power Limit 1
Figure 7-32
14
15
Power Limit
VCC Plane Power Limit
Enable
Figure 7-33. The units for the Power
46
47
Power Limit
Enable #2
14
15
Power Limit
Enable #1
should be set to activate
32
Power Limit # 2
Power Limit # 1
0
0
77