Table 3: Data & Clock Outputs Vs Demodulation - Safran CORTEX Series User Manual

OUTPUT MODE
CLK+
J10 / J11
CLK-
OUT1+
J12 / J13
OUT1-
OUT2+
J14 / J15
OUT2-
OUT3+
J16 / J17
OUT3-
CLK+
J20 / J21
CLK-
OUT1+
J22 / J23
OUT1-
OUT2+
J24 / J25
OUT2-
OUT3+
J26 / J27
OUT3-
* BPSK demodulation can be set to SPLIT2 mode with high rates hardware menus (single demodulator).
In this case the data stream is split on the two outputs J12/ J13 and J22/J23.
© Safran Data Systems – IMP000074 e14r1
HIGH DATA RATE RECEIVER
HDR-4G+ USER'S MANUAL
BPSK QPSK
8PSK
16QAM
SPLIT 2
Clock @ BR Clock @ BR/2
Demod A Demod A
Data Data I
Reserved Data Q
Clock @ BR Clock @ BR/2
Demod A Demod A
Clock @ BR Clock @ BR/2
Demod B Demod B
Data Data I
Reserved Data Q
Clock @ BR Clock @ BR/2
Demod B Demod B
Table 3: Data & Clock Outputs vs Demodulation
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Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
QPSK QPSK
8PSK 8PSK
16QAM 16QAM
I/QMERGE SPLIT 4
Clock @ BR
Clock @ BR /4
Demod A
Data Data I -1
Data Data Q -1
Clock @ BR
Clock @ BR/4
Demod A
Clock @ BR
reserved
Demod B
Data Data I - 2
Data Data Q - 2
Clock @ BR
Reserved
Demod B
Safran Data Systems
A/UQPSK
Clock @ BR I
Demod A
Data I
Data Q
Clock @ BR Q
Demod A
Clock @ BR I
Demod B
Data I
Data Q
Clock @ BR Q
Demod B
.
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