Cortex Hdr Architecture; Functional Block Diagram Of A Demodulation Channel; Figure 1: Cortex Hdr Demodulation And Ingestion Functional Block Diagram - Safran CORTEX Series User Manual

1.4

CORTEX HDR Architecture

1.4.1

Functional Block Diagram of a Demodulation Channel

Analog Processing
IF Inputs
(2 IF inputs)
A/D Conversion
5/10 MHz Input
Time Frequency
&
Distribution
Time Code Input

Figure 1: CORTEX HDR Demodulation and Ingestion Functional Block Diagram

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HIGH DATA RATE RECEIVER
HDR-4G+ USER'S MANUAL
Vector Demodulation
(1 to 8 2 demod )
BPSK, QPSK,
O/S/U/A/QPSK
SOQPSK 8PSK
16QAM/16...256APSK
Rejection & Matched filter
I&D
RRC /GMSK / SOQPSK filters
EQUALIZATION
DEAF XDEAF
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Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
Digital Outputs
Data + Clock
Generation
Optional
Bit
Viterbi
Sync
or TCM
PCM
decoding
Decoding
Optional ingestion:
Frame Synchronization
Time Tagging
Real Time TCP/IP UDT
Data Storage
Internal SSD
BER Measurement
Vector Analysis
Spectrum Analysis
Automatic filter display
Monitoring & Control
Monitoring & Control
Software Package (MCS)
Graphical User Interface
(Free Copyright)
Safran Data Systems
Optional
CADU
RS or LDCP
Decoding
Descrambling
Transport layer
SCSI output
Ethernet LAN
.
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