Safran CORTEX Series User Manual page 15

Figure 1: CORTEX HDR Demodulation and Ingestion Functional Block Diagram ........................................................... 34
Figure 2: CORTEX HDR Test Modulator Functional Block Diagram (single channel, single IF) ..................................... 35
Figure 3: CORTEX HDR Test Modulator - Multi channel, multi IF operation .................................................................. 35
Figure 4: CORTEX HDR Hardware Block Diagram .......................................................................................................... 36
Figure 5: Example of CORTEX HDR Workstation ............................................................................................................ 37
Figure 6: MCS Software Version ........................................................................................................................................ 40
Figure 7: CORTEX HDR TCP-IP Interfaces ...................................................................................................................... 42
Figure 8: Demodulator input stage with separate IF inputs ................................................................................................. 59
Figure 9: CORTEX HDR Test Modulator - Multi channel, multi IF operation .................................................................. 60
Figure 10: CORTEX HDR 4G/G+ I/Os .............................................................................................................................. 61
Figure 11: Soft Decision Coding vs I/Q Constellation (Normal Soft Output) ..................................................................... 68
Figure 12: Soft Decision Coding vs I/Q Constellation (Merge Soft Output) ...................................................................... 69
Figure 13: Effect of the DEAF. ........................................................................................................................................... 82
Figure 14: Effect of the XDEAF. ........................................................................................................................................ 85
Figure 15: Viterbi Decoding Module. Single & Dual Operating Modes ............................................................................. 87
Figure 16: Parallel Viterbi Decoding Module. .................................................................................................................... 88
Figure 17: Viterbi De-puncturing Process. .......................................................................................................................... 89
Figure 18: Punctured Viterbi BER Performances ................................................................................................................ 90
Figure 19: Structure of the 4D 8PSK-TCM Coder/Mapper ................................................................................................. 97
Figure 20: Differential Coder and Modulo-8 Adder Principle ............................................................................................ 98
Figure 21: Convolutional Coder Recommended for High Data Rates ................................................................................ 98
Figure 22: Constellation Mapper for 2 bits/channel-symbol ............................................................................................... 99
Figure 23: Constellation Mapper for 2.25 bits/channel-symbol ........................................................................................ 100
Figure 24: Constellation mapper for 2.5 bits/channel-symbol ........................................................................................... 101
Figure 25: Constellation Mapper for 2.75 bits/channel-symbol ........................................................................................ 101
Figure 26: Coder and Mapper Implementation at 2 bits/channel-symbol Efficiency ........................................................ 102
Figure 27: Coder and Mapper Implementation at 2.25 bits/channel-symbol Efficiency ................................................... 102
Figure 28: Coder and Mapper Implementation at 2.5 bits/channel-symbol Efficiency ..................................................... 103
Figure 29: Coder and Mapper Implementation at 2.75 bits/channel-symbol Efficiency ................................................... 103
Figure 30: Concatenation Principle ................................................................................................................................... 104
Figure 31: Randomization Principle .................................................................................................................................. 105
Figure 32: Data Arrangement in TCM 2.5 bits/channel_symbol ....................................................................................... 107
Figure 33: BER Measurement Methods: Tested ambiguities and GUI display ................................................................. 109
Figure 34: Typical Es/N0 estimation over the constellation .............................................................................................. 118
Figure 35: Estimator behavior VS Es/N0 and modulations ............................................................................................... 119
Figure 36: Standard Es/N0 estimate in the GUI ................................................................................................................ 119
Figure 37: Standard Es/N0 estimate in the vector pane ..................................................................................................... 120
Figure 38: data-aided estimation of Es/N0 ........................................................................................................................ 121
Figure 39: data-aided estimator in the GUI, Physical Layer pane of the demodulator ...................................................... 122
Figure 40: Data Processing Unit Block Diagram .............................................................................................................. 123
Figure 41: Frame Synchronization Process ....................................................................................................................... 125
Figure 42: Data Transmission over TCP-IP. Message Formatting .................................................................................... 132
Figure 43: Recorded Data File Structure ........................................................................................................................... 134
Figure 44: CCSDS FTP Mode Storage Directories ........................................................................................................... 136
Figure 45: Playback function: Test Modulator operating mode ........................................................................................ 138
Figure 46: Playback function: Test Modulator Data + Clock mode .................................................................................. 138
Figure 47: QPSK demodulation with 2 DPU..................................................................................................................... 140
Figure 48: QPSK or 16QAM demodulation with 4 DPU .................................................................................................. 141
Figure 49: 16QAM demodulation with 8 DPU ................................................................................................................. 142
Figure 50: QPSK or 16QAM demodulation with 1 DPU .................................................................................................. 143
Figure 51: QPSK demodulation with 2 DPU..................................................................................................................... 143
© Safran Data Systems - IMP000074 e14r1
HIGH DATA RATE RECEIVER
HDR-4G+ USER'S MANUAL
LIST OF FIGURES
This document is the property of
It cannot be duplicated or distributed without expressed written consent.
Ref. DTU 100782
Is.Rev 3.5
Date: June 1, 2021
Safran Data Systems
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