Ldpc Decoding; Introduction; Ldpc 7/8 For Near-Earth Applications; Ar4Ja Ldpc ½, 2/3, 4/5 Codes For Deep Space Applications - Safran CORTEX Series User Manual

3.4.10

LDPC Decoding

3.4.10.1

Introduction

Low Density Parity Check codes are powerful linear block codes. They are defined by their parity check
matrix. The construction of these codes involves the juxtaposition of smaller cyclic sub-matrices.
Nowadays, iterative algorithms, which offer near-optimum performance at a manageable complexity,
are used for the decoding of large linear LDPC codes.
In conformity with the CCSDS experimental specification, the CORTEX HDR supports:
- the 7/8 LDPC code optimized for near-earth applications
the 1/2 and 2/3 LDPC codes optimized for deep space applications
-
For more details on these codes, refer to the following CCSDS document:
Low Density Parity Check codes for use in near-earth and deep space applications
Experimental Specification - CCSDS 131.1-O-2
September 2007
3.4.10.2

LDPC 7/8 for near-earth applications

As specified by the CCSDS, the implemented (8160, 7136) LDPC code is a shortened version of the
baseline (8176, 7156) LPC code, i.e.
information block length k: 7136 bits (892 bytes)
-
code block length n: 8176 bits (1022 bytes)
-
3.4.10.3 AR4JA LDPC ½, 2/3, 4/5 codes for deep space applications
The Cortex HDR supports a subset of the LDPC codes family optimized for deep space applications
and specified by CCSDS. These codes are also known as AR4JA LDPC codes.
The supported codes are the following:
 1/2 rate LDPC 1K code
 1/2 rate LDPC 4K code
 1/2 rate LDPC 16K code
 2/3 rate LDPC 4K code
 2/3 rate LDPC 16K code
 4/5 rate LDPC 4K code
 4/5 rate LDPC 16K code
3.4.10.4

Implementation

The LDPC decoder is implemented after a frame synchronizer and after the de-randomizer if the
randomization is used. The LDPC is a block decoder that can be synchronized to CADU processing
and when it is, from this aspect it is identical to the Turbo decoding and very close to the Reed
Solomon decoding. The LDPC code can also be asynchronous from the CADU (refer to § 1.6.1.7
Transport layer (RSDVB or asynchronous LDPC layer)).
 Any phase ambiguity at the output of the demodulation has to be resolved by the frame
synchronizer before the decoding
 The decoder uses soft decision at the output of the bit synchronizer
 If a de-randomizer is used, this one has to work on soft decision
The LDPC decoding is implemented as an iterative process with parity decoding.
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