Table 14: Modulations And Input Modes; Table 15: Connectors Allocation, Single Ended Ecl - Safran CORTEX Series User Manual

When the board is fitted with differential ECL the only mode available is Serial data mode as only
one data input is available. In this case the serial data mode is forced, regardless of the setting that is
set in the configuration table.
Here are the possible schemes depending on the modulation and the data type:
M
ODULATION
BPSK
QPSK
OQPSK
8PSK
16QAM
16APSK
32APSK
64APSK
Here is the table of connector allocation depending on the data scheme, for single ended ECL:
L ID
ABEL
ECL IN 1 J52
ECL IN 2 J53
ECL IN 3 J54
ECL IN 4 J55
ECL IN 5 J56
(1): I/Q/Z/X data refers to direct symbol mapping. For example, I/Q/Z mode in 8PSK means that each
bit fed to the input will be directly used to map the symbol using the mapping selected in the connected
MDU. In BPSK, only I is relevant. In QPSK/OQPSK, I and Q are relevant. In 8PSK I, Q, and Z are
relevant. In 16APSK and 16QAM, I, Q, Z and X are relevant.
(2): the convention for data merging is D1 D2 D3 D4, D1 being the MSB and first bit transmitted.
© Safran Data Systems – IMP000074 e14r1
HIGH DATA RATE RECEIVER
HDR-4G+ USER'S MANUAL
H
ARD
(
SINGLE ENDED
Yes, I data
Yes, IQ data
Yes, IQ data
Yes, IQZ data
Yes, IQZX
Yes, IQZX

Table 14: modulations and input modes

H S S
ARD YMBOL ERIAL
(1)
I data Data
(1)
Q data -
(1)
Z data -
(1)
X data -
Clock
Clock

Table 15: connectors allocation, single Ended ECL

Ref.
Is.Rev
Date:
S
YMBOL
ECL )
ONLY
introduced internally to the
No
No
//2
DATA
(2)
D1
(2)
D2
-
-
Clock
Safran Data Systems
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It cannot be duplicated or distributed without expressed written consent.
DTU 100782
3.5
June 1, 2021
O
THERS
Yes
Yes
Yes, single clock, offset
modulator.
Yes
Yes
Yes
Yes
Yes
//3 //4
DATA
(2)
D1 D1
(2)
D2 D2
(2)
D3 D3
- D4
Clock Clock
.
DATA
(2)
(2)
(2)
(2)
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