Emac Control Module Receive Threshold Interrupt Status Register (Cmrxthreshintstat); Emac Control Module Receive Threshold Interrupt Status Register (Cmrxthreshintstat) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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3.3.1.9

EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)

The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in
described in Table
Figure 3-20. EMAC Control Module Receive Threshold Interrupt Status Register
31
15
Reserved
LEGEND: R = Read only; -n = value after reset
Table 3-19. EMAC Control Module Receive Threshold Interrupt Status Register
Bit Field
31-8 Reserved
7-0 C_RX_THRESH_STAT
SPRUGX9 – 15 April 2011
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Preliminary
3-19.
(CMRXTHRESHINTSTAT)
R-0
(CMRXTHRESHINTSTAT) Field Descriptions
Value Description
0 Reserved
0-FFh Core 0 Receive Threshold Masked Interrupt Status.
Each bit in this read only register corresponds to the bit in the receive threshold interrupt
that is enabled and generating an interrupt on C0_RX_THRESH_PULSE.
© 2011, Texas Instruments Incorporated
Reserved
R-0
8 7
C_RX_THRESH_STAT
Registers
Figure 3-20 and
R/W-0
EMAC/MDIO Module
16
0
461