Reset - Altera Cyclone V User Manual

November 2011
1101
This chapter covers the functional aspects of the reset and clock circuitry for the
Cyclone V Hard IP for PCI Express. It includes the following sections:

Reset

■
■ Clocks
For descriptions of the available reset and clock signals refer to the following sections:
"Reset Signals" on page
Reset
The Cyclone V Hard IP for PCI Express IP core includes an embedded reset controller
to handle the initial reset of the PMA, PCS, and Hard IP for PCI Express IP core. The
pin_perst signal which is driven from one of the two designated nPERST pins of the
device initiates reset.
Figure 7–1. Reset Controller for Cyclone V Devices
npor
pin_perst
Reset
Controller
frefclk
(derived from
refclk )
busy_xcvr_reconfig
Transceiver
Reconfiguration
Controller
As Figure 7–1
LTSSM state from the Hard IP and drives global and specialized resets to the Hard IP.
After reset is complete, all port registers and state machines are set to their
initialization values with the exception of sticky registers as defined Sections 7.4 and
7.6 of the
varying amounts of the state of the Hard IP block as follows:
November 2011 Altera Corporation
5–14, and
Figure 7–1 provides a high-level view of the reset hardware.
<variant>.v or .vhd
rst
npor
crst
srst
indicates, the reset controller receives information about the current
PCI Express Base Specification. The reset outputs of the reset controller affect
7. Reset and Clocks
"Clock Signals" on page
Transceiver Reset
State Machine
Configuration Space
Sticky Registers
Configuration Space
Non-Sticky Registers
Datapath State Machines of
MegaCore Function
5–14.
l2_exit
hotrst_exit
dlup_exit
dlup
serdes_pll_locked
pld_clk_inuse
pld_core_ready
fixedclk_locked
ltssmstate[4:0]
Cyclone V Hard IP for PCI Express