Altera Cyclone V User Manual page 68

5–16
Table 5–6. Reset and Link Training Signals (Part 3 of 3)
Signal I/O
O
currentspeed[1:0]
O
dl_ltssm[4:0]
Cyclone V Hard IP for PCI Express
Indicates the current speed of the PCIe link. The following encodings are defined:
2b'00: Reserved
■
2b'01: Gen1
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2b'10: Gen2
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2b'11: Gen3
■
LTSSM state: The LTSSM state machine encoding defines the following states:
00000: detect.quiet
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00001: detect.active
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00010: polling.active
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00011: polling.compliance
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00100: polling.configuration
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00101: polling.speed
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00110: config.linkwidthstart
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00111: config.linkaccept
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01000: config.lanenumaccept
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01001: config.lanenumwait
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01010: config.complete
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01011: config.idle
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01100: recovery.rcvlock
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01101: recovery.rcvconfig
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01110: recovery.idle
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01111: L0
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10000: disable
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10001: loopback.entry
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10010: loopback.active
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10011: loopback.exit
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10100: hot.reset
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10101: L0s
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10110: L1.entry
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10111: L1.idle
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11000: L2.idle
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11001: L2.transmit.wake
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11010: recovery.speed
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Chapter 5: IP Core Interfaces
Description
November 2011 Altera Corporation
Reset Signals