Physical Layer Errors; Data Link Layer Errors - Altera Cyclone V User Manual

12–2

Physical Layer Errors

Table 12–2
P
Table 12–2. Errors Detected by the Physical Layer
Error
Receive port error
Note to Table 12–2:
(1) Considered optional by the PCI Express specification.

Data Link Layer Errors

Table 12–3
Table 12–3. Errors Detected by the Data Link Layer
Error
Bad TLP
Bad DLLP
Replay timer
Replay num rollover
Data Link Layer protocol
Cyclone V Hard IP for PCI Express
describes errors detected by the Physical Layer.
(1)
Type
This error has the following 3 potential causes:
Physical coding sublayer error when a lane is in L0 state. These errors
■
are reported to the Hard IP block via the per lane PIPE interface input
receive status signals, rxstatus<lane_number>[2:0] using the
following encodings:
100: 8B/10B Decode Error
Correctable
101: Elastic Buffer Overflow
110: Elastic Buffer Underflow
111: Disparity Error
Deskew error caused by overflow of the multilane deskew FIFO.
■
Control symbol received in wrong lane.
■
describes errors detected by the Data Link Layer.
Type
This error occurs when a LCRC verification fails or when a sequence
Correctable
number error occurs.
Correctable This error occurs when a CRC verification fails.
Correctable This error occurs when the replay timer times out.
Correctable This error occurs when the replay number rolls over.
This error occurs when a sequence number specified by the Ack/Nak
Uncorrectable
block in the Data Link Layer (AckNak_Seq_Num) does not correspond to
(fatal)
an unacknowledged TLP. (Refer to
Chapter 12: Error Handling
Physical Layer Errors
Description
Description
"Data Link Layer" on page
November 2011 Altera Corporation
4–6.)