Altera Cyclone V User Manual page 40

3–8
1
When you click on a Func<n> tab under the Port Functions heading, the parameter
settings automatically relate to the function currently selected.
Base Address Registers for Function <n>
Table 3–7
Table 3–7. Func0–Func7 BARs and Expansion ROM
Parameter
Type
64-bit prefetchable memory
0x010, 0x014,
32-bit non-prefetchable memory
0x018, 0x01C,
32-bit prefetchable memory
0x020, 0x024
I/O address space
Size 16 Bytes–8 EBytes
Size
4 KBytes–16 MBytes
Base and Limit Registers for Root Port Func <n>
If you specify a Root Port for function 0, the settings for Base and Limit Registers
required by Root Ports appear after the Base Address Register heading. These
settings are stored in the Type 1 Configuration Space for Root Ports. They are used for
TLP routing and specify the address ranges assigned to components that are
downstream of the Root Port or bridge. Function 0 is the only function that provides
the Root Port option for Port type.
f
For more information, refer to the
Table 3–8
Table 3–8. Base and Limit Registers
Parameter
Input/Output
Prefetchable memory
Cyclone V Hard IP for PCI Express
describes the Base Address (BAR) register parameters.
Value
If you select 64-bit prefetchable memory, 2 contiguous BARs are
combined to form a 64-bit prefetchable BAR; you must set the
higher numbered BAR to Disabled. A non-prefetchable 64-bit BAR
Disabled
is not supported because in a typical system, the Root Port Type 1
Configuration Space sets the maximum non-prefetchable memory
window to 32-bits. The BARs can also be configured as separate
32-bit prefetchable or non-prefetchable memories.
The I/O address space BAR is only available for the Legacy
Endpoint.
The Endpoint and Root Port variants support the following memory
sizes:
×1, ×4: 128 bytes–2 GBytes or 8 EBytes
■
The Legacy Endpoint supports the following I/O space BARs:
×1, ×4:16 bytes–4 KBytes
■
Expansion ROM
Disabled
Specifies the size of the optional ROM.
describes the Base and Limit registers parameters.
Value
Disable
Specifies the address widths for the IO base and IO limit
16-bit I/O addressing
registers.
32-bit I/O addressing
Disable
Specifies the address widths for the Prefetchable Memory
32-bit I/O addressing
Base register and Prefetchable Memory Limit register.
64-bit I/O addressing
Description
PCI-to-PCI Bridge Architecture
Description
Chapter 3: Parameter Settings
Port Functions
Specification.
November 2011 Altera Corporation