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Cyclone V E FPGA Development Board Reference Manual Cyclone V E FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01075-1.4 Feedback Subscribe Arrow.com. Downloaded from...
The Cyclone V E FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V E FPGA. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V E FPGA designs.
Chapter 1: Overview Board Component Blocks Board Component Blocks The development board features the following major component blocks: ■ One Cyclone V E FPGA (5CEFA7F31I7N) in a 896-pin FineLine BGA (FBGA) package 149,500 LEs ■ 56,480 adaptive logic modules (ALMs) ■...
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■ Power supply ■ 14–20-V (laptop) DC input ■ ■ Mechanical 6.5" x 4.5" size board ■ August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from...
Chapter 1: Overview Development Board Block Diagram Development Board Block Diagram Figure 1–1 shows a block diagram of the Cyclone V E FPGA development board. Figure 1–1. Cyclone V E FPGA Development Board Block Diagram Clock Enable Connector Clock In...
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2. Board Components This chapter introduces the major components on the Cyclone V E FPGA development board. Figure 2–1 illustrates the component locations and Table 2–1 provides a brief description of all component features of the board. A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Cyclone V E FPGA development kit documents directory.
2–2 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Cyclone V E FPGA development board, including an annotated board image and component descriptions. Figure 2–1 shows an overview of the board features. Figure 2–1. Overview of the Cyclone V E FPGA Development Board Features...
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Two 256-MB DDR3 SDRAM with a 16-bit data bus. 512-MB LPDDR 2 SDRAM with 32-bit bus, only 16-bit bus is used on LPDDR2 x 16 memory this board. August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com.
DC input jack. Featured Device: Cyclone V E FPGA The Cyclone V E FPGA development board features a Cyclone V E FPGA 5CEFA7F31I7N device (U1) in a 896-pin FBGA package. For more information about Cyclone V device family, refer to the Cyclone V Device Handbook.
The Cyclone V E FPGA 5CEFA7F31I7N device has total of 480 user I/Os. Table 2–3 lists the Cyclone V E FPGA I/O pin count and usage by function on the board. Table 2–3. Cyclone V E FPGA I/O Pin Count...
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Altera Design Store. In the Cyclone V E FPGA Development Kit, under Design Examples, click Cyclone V E FPGA Development Kit Baseline Pinout. Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)
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FPGA partial reconfiguration request FPGA_PR_REQUEST 3.3-V FPGA configuration chip select FPGA_MAX_NCS 2.5-V FSM address bus FSM_A1 2.5-V FSM address bus FSM_A2 August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
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FSM data bus FSM_D11 2.5-V FSM data bus FSM_D12 2.5-V FSM data bus FSM_D13 2.5-V FSM data bus FSM_D14 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
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2.5-V Power monitor SPI clock SENSE_SCK 2.5-V Power monitor SPI data in SENSE_SDI 2.5-V Power monitor SPI data out SENSE_SDO August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
FPGA Programming over Embedded USB-Blaster II This configuration method implements a USB type-B connector (J10), a USB 2.0 PHY device (U18), and an Altera MAX II CPLD EPM570GF100I5N (U16) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB type-B connector on the board and a USB port of a PC running the Quartus II software.
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GUI interfaces. Table 2–5 lists the USB 2.0 PHY schematic signal names and their corresponding Cyclone V E FPGA pin numbers. Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2) Board Reference Schematic...
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Write strobe for slave FIFO FX2_SLWRN — 3.3-V USB 2.0 PHY wake signal FX2_WAKEUP AA23 3.3-V USB 2.0 PHY 48-MHz interface clock USB_CLK Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash memory device. This...
For more information on the following topics, refer to the respective documents: Board Update Portal, PFL design, and flash memory map storage, refer to the ■ Cyclone V E FPGA Development Kit User Guide. PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.
AS mode, resistor rework needs to be done. Configure the MSEL setting using the MSEL DIP switch (SW1) to change the configuration scheme. Figure 2–5 shows the connection between the EPCQ and the Cyclone V E FPGA. Figure 2–5. EPCQ Configuration CCPGM 10 kΩ...
JTAG settings DIP switch CPU reset push button ■ ■ MAX V reset push button ■ Program configuration push button Program select push button ■ Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
RESERVED CPU Reset Push Button The CPU reset push button, CPU_RESETn (S4), is an input to the Cyclone V E FPGA DEV_CLRn pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD 5M2210 System Controller also drives this push button during power-on-reset (POR).
This section describes the board's clock inputs and outputs. On-Board Oscillators The development board include oscillators with a frequency of 50-MHz, 100-MHz, and a programmable oscillator. Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com.
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Chapter 2: Board Components 2–19 Clock Circuitry Figure 2–6 shows the default frequencies of all external clocks going to the Cyclone V E FPGA development board. Figure 2–6. Cyclone V E FPGA Development Board Clocks CLK_USB FA-128 SG-310DF 10/100/1000 Cypress...
Board references S5, S6, S7, and S8 are push buttons for controlling the FPGA designs that loads into the Cyclone V E FPGA device. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1.
LEDs from the designs loaded into the Cyclone V E FPGA. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.
Table 2–17 summarizes the character LCD pin assignments. The signal names and directions are relative to the Cyclone V E FPGA device. Table 2–17. Character LCD Pin Assignments, Schematic Signal Names, and Functions Board Cyclone V E FPGA...
Single-ended signal for debug purposes only HEADER_D4 1.5-V Single-ended signal for debug purposes only HEADER_D5 1.5-V Single-ended signal for debug purposes only HEADER_D6 August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Pseudo-differential signals for debug purposes only HEADER_N5 Components and Interfaces This section describes the development board's communication ports and interface cards relative to the Cyclone V E FPGA device. The development board supports the following communication ports: ■ RS-232 Serial UART ■...
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25-MHz RGMII transmit clock ENETA_XTAL_25MHZ — 2.5-V CMOS Media dependent interface ENETA_MDI_P0 — 2.5-V CMOS Media dependent interface ENETA_MDI_N0 August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
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2.5-V CMOS Media dependent interface ENETB_MDI_N1 — 2.5-V CMOS Media dependent interface ENETB_MDI_P2 — 2.5-V CMOS Media dependent interface ENETB_MDI_N2 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series. Since the Cyclone V E FPGA development board is not a transceiver board, the transceiver pins of the HSMC is not connected to the Cyclone V E FPGA device.
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LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19 HSMC_RX_D_N3 AH24 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20 HSMC_TX_D_P4 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com.
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LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57 HSMC_RX_D_P12 AH20 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58 HSMC_TX_D_N12 August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Table 2–24 lists the RS-232 serial UART pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–22. RS-232 Serial UART Schematic Signal Names and Functions...
Table 2–23 lists the USB-UART pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–23. USB-UART Schematic Signal Names and Functions...
Table 2–24 lists the DDR3 pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
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SSTL Class I Differential 1.5-V Data strobe N byte lane 1 DDR3_DQS_N1 SSTL Class I 1.5-V SSTL Class I On-die termination enable DDR3_ODT August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
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Data bus byte lane 2 DDR3_DQ22 1.5-V SSTL Class I Data bus byte lane 2 DDR3_DQ23 1.5-V SSTL Class I Data bus byte lane 3 DDR3_DQ24 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Table 2–25 lists the LPDDR2 SDRAM pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–25. LPDDR2 SDRAM Schematic Signal Names and Functions...
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Data bus byte lane 3 LPDDR2_DQ26 — 1.2-V HSUL Data bus byte lane 3 LPDDR2_DQ27 — 1.2-V HSUL Data bus byte lane 3 LPDDR2_DQ28 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
I Table 2–26 lists the EEPROM pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–26. EEPROM Schematic Signal Names and Functions...
FSM_D1 2.5-V Data bus FSM_D2 2.5-V Data bus FSM_D3 2.5-V Data bus FSM_D4 2.5-V Data bus FSM_D5 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Table 2–28 lists the flash pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V E FPGA in terms of I/O setting and direction. Table 2–28. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
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FSM_D2 2.5-V Data bus FSM_D3 2.5-V Data bus FSM_D4 2.5-V Data bus FSM_D5 2.5-V Data bus FSM_D6 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
65 W. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors. An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails. August 2017 Altera Corporation Cyclone V E FPGA Development Board Reference Manual Arrow.com. Arrow.com. Arrow.com.
5.37 V LDO 5.37 V at 0.3 mA FPGA Power Rails Power 20 mA, +/- 5% Monitor Board Main Power Rails LT3009 Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
3. Board Components Reference This chapter describes the Cyclone V E FPGA development board components, the manufacturing information, and the board compliance statements. Board Components Table lists the component reference and manufacturing information of all the components on the development board.
(EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user. Cyclone V E FPGA Development Board August 2017 Altera Corporation Reference Manual Arrow.com.
Additional Information This chapter provides additional information about the document and Altera. Board Revision History The following table lists the versions of all releases of the Cyclone V E FPGA Development Board. Release Date Version Description New board revision. New device part number—5CEFA7F31I7N.
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