Altera Stratix V Hard IP Board Manuals

Manuals and User Guides for Altera Stratix V Hard IP Board. We have 1 Altera Stratix V Hard IP Board manual available for free PDF download: User Manual

Altera Stratix V Hard IP User Manual (232 pages)

for PCI Express

Brand: Altera | Category: Motherboard | Size: 6 MB

Table of Contents
3
Chapter 1. Datasheet

9
- Features
  9
- Release Information
  12
- Device Family Support
  13
- Configurations
  13
- Debug Features
  14
- IP Core Verification
  14
  - Compatibility Testing Environment
    15
- Performance and Resource Utilization
  15
- Recommended Speed Grades
  16
Chapter 2 .Getting Started with the Stratix V Hard IP for PCI Express

21
Chapter 3 .Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express

41
Chapter 4. Parameter Settings

53
Chapter 5. IP Core Architecture

65
- Key Interfaces
  67
  - Avalon-ST Interface
    67
    
    RX Datapath
    67
    
    TX Datapath
    67
  - Avalon-MM Interface
    68
  - Clocks and Reset
    68
  - Local Management Interface (LMI Interface)
    68
  - Hard IP Reconfiguration
    68
  - Transceiver Reconfiguration
    68
  - Interrupts
    69
  - Pipe
    69
- Transaction Layer
  69
  - Configuration Space
    70
- Data Link Layer
  71
- Physical Layer
  73
- PCI Express Avalon-MM Bridge
  75
- Completer Only Single Dword Endpoint
  81
  - RX Block
    82
  - Avalon-MM RX Master Block
    83
  - TX Block
    83
  - Interrupt Handler Block
    83
Chapter 6. IP Core Interfaces

85
Chapter 7. Register Descriptions

149
Chapter 8. Reset and Clocks

169
- Reset
  169
- Clocks
  173
  - Stratix V Hard IP for PCI Express Clock Domains
    173
    
    P_Clk
    174
    
    Coreclkout
    174
    
    Pld_Clk
    175
  - Additional Clocks
    175
    
    Hip_Reconfig_Clk
    175
    
    Reconfig_Xcvr_Clk
    175
  - Clock Summary
    175
Chapter 9 .Transaction Layer Protocol (TLP) Details

177
- Supported Message Types
  177
- Transaction Layer Routing Rules
  179
- Receive Buffer Reordering
  180
Chapter 10. Optional Features

183
- Configuration Via Protocol (Cvp)
  183
- Ecrc
  184
  - ECRC on the RX Path
    184
  - ECRC on the TX Path
    185
- Lane Initialization and Reversal
  186
Chapter 11. Interrupts

187
Chapter 12. Flow Control

195
- Throughput of Posted Writes
  195
- Throughput of Non-Posted Reads
  197
Chapter 13. Error Handling

199
- Physical Layer Errors
  200
- Data Link Layer Errors
  200
- Transaction Layer Errors
  201
- Error Reporting and Data Poisoning
  203
- Uncorrectable and Correctable Error Status Bits
  204
Chapter 14. Hard IP Reconfiguration and Transceiver Reconfiguration

205
- Hard IP Reconfiguration Interface
  205
- Transceiver PHY IP Reconfiguration
  213
  - Connecting the Transceiver Reconfiguration Controller IP Core
    213
  - Learning more about Transceiver PHY Reconfiguration
    215
Chapter 15. Debugging

217
- Hardware Bring-Up Issues
  217
- Link Training
  217
- Link Hangs in L0 Due to Deassertion of Tx_St_Ready
  220
  - Use Third-Party Pcie Analyzer
    224
  - BIOS Enumeration Issues
    224
Appendix A.transaction Layer Packet (TLP) Header Formats

225
- TLP Packet Format Without Data Payload
  225
- TLP Packet Format with Data Payload
  227
Additional Information

229
- Revision History
  229

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Altera Stratix V Hard IP Board Manuals

Altera Stratix V Hard IP User Manual (232 pages)

Table of Contents

Chapter 1. Datasheet

Chapter 2 .Getting Started with the Stratix V Hard IP for PCI Express

Chapter 3 .Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express

Chapter 4. Parameter Settings

Chapter 5. IP Core Architecture

Chapter 6. IP Core Interfaces

Chapter 7. Register Descriptions

Chapter 8. Reset and Clocks

Chapter 9 .Transaction Layer Protocol (TLP) Details

Chapter 10. Optional Features

Chapter 11. Interrupts

Chapter 12. Flow Control

Chapter 13. Error Handling

Chapter 14. Hard IP Reconfiguration and Transceiver Reconfiguration

Chapter 15. Debugging

Appendix A.transaction Layer Packet (TLP) Header Formats

Additional Information

Related Products

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