Altera Cyclone V User Manual page 58

5–6
1
The Avalon-ST protocol, as defined in
while the Hard IP for PCI Express packs symbols into words in little endian format.
Consequently, you cannot use the standard data format adapters available in Qsys.
Figure 5–3. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLP with Non-Qword Aligned Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
Figure 5–4
three dword header with qword aligned addresses. Note that the byte enables
indicate the first byte of data is not valid and the last dword of data has a single valid
byte.
Figure 5–4. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLP with Qword Aligned Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
Figure 5–5
for a four dword header with qword aligned addresses with a 64-bit bus.
Figure 5–5. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLP with Qword Aligned Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
Cyclone V Hard IP for PCI Express
Header1
Header0
illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
Header 1
Header 0 Header2
shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs
header1
header0
Avalon Interface Specifications, is big endian,
Data0
Header2
Data1 Data3
Data0 Data2
F 1
E F
header3
header2
Chapter 5: IP Core Interfaces
Avalon-ST RX Interface
Data2
Data1
data1
data0
F
F
November 2011 Altera Corporation