Altera Cyclone V User Manual page 61

Chapter 5: IP Core Interfaces
Avalon-ST TX Interface
Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 2 of 3)
Signal
(1)
tx_st_ready
(1)
tx_st_valid
tx_st_err
tx_cred_datafccp
tx_cred_datafcnp
tx_cred_datafcp
November 2011 Altera Corporation
Avalon-ST
Width Dir
Type
Indicates that the Transaction Layer is ready to accept data
for transmission. The core deasserts this signal to throttle
the data stream. tx_st_ready may be asserted during
reset. The Application Layer should wait at least 2 clock
cycles after the reset is released before issuing packets on
the Avalon-ST TX interface. The reset_status signal can
also be used to monitor when the Hard IP has come out of
reset.
1 O
ready
If tx_st_ready is asserted by the Transaction Layer on
cycle <n>, then <n + readyLatency> is a ready cycle,
during which the Application Layer may assert valid and
transfer data.
When tx_st_ready, tx_st_valid and tx_st_data are
registered (the typical case), Altera recommends a
readyLatency of 2 cycles to facilitate timing closure;
however, a readyLatency of 1 cycle is possible.
Clocks tx_st_data to the Hard IP when tx_st_ready is
also asserted. Between tx_st_sop and tx_st_eop,
tx_st_valid can be asserted only if tx_st_ready is
asserted. When tx_st_ready deasserts, this signal must
deassert within 1 or 2 clock cycles. When tx_st_ready
reasserts, and tx_st_data is in mid-TLP, this signal must
1 I
valid
reassert within 2 cycles. Refer to
page 5–13
To facilitate timing closure, Altera recommends that you
register both the tx_st_ready and tx_st_valid signals.
If no other delays are added to the ready-valid latency, the
resulting delay corresponds to a readyLatency of 2.
Indicates an error on transmitted TLP. This signal is used to
nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert
this signal for 1 cycle after the SOP and before the EOP.
1 I
error
When a packet is nullified, the following packet should not
be transmitted until the next clock cycle. tx_st_err is not
available for packets that are 1 or 2 cycles long. The error
signal must be asserted while the valid signal is asserted.
Component Specific Signals
Data credit limit for the received FC completions. Each
component
12 O
credit is 16 bytes.
specific
Data credit limit for the non-posted requests. Each credit is
component
12 O
16 bytes.
specific
Data credit limit for the FC posted writes. Each credit is 16
component
12 O
bytes.
specific
Description
Figure 5–12 on
for the timing of this signal.
Cyclone V Hard IP for PCI Express
5–9
User Guide