Transaction Layer Routing Rules - Altera Cyclone V User Manual

Hard ip for pci express
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Chapter 8: Transaction Layer Protocol (TLP) Details

Transaction Layer Routing Rules

Table 8–1. Supported Message Types
Root
Message
Port
Attention_indicator On Transmit
Attention_Indicator
Transmit
Blink
Attention_indicator_
Transmit
Off
Power_Indicator On
Transmit
Power_Indicator Blink
Transmit
Power_Indicator Off
Transmit
Attention
Receive
(1)
Button_Pressed
Notes to
Table
8–1:
(1) In Endpoint mode.
(2) In the
PCI Express Base Specification Revision
Transaction Layer Routing Rules
Transactions adhere to the following routing rules:
In the receive direction (from the PCI Express link), memory and I/O requests that
match the defined base address register (BAR) contents and vendor-defined
messages with or without data route to the receive interface. The Application
Layer logic processes the requests and generates the read completions, if needed.
In Endpoint mode, received Type 0 Configuration requests from the PCI Express
upstream port route to the internal Configuration Space and the Cyclone V Hard
IP for PCI Express generates and transmits the completion.
The Hard IP handles supported received message transactions (Power
Management and Slot Power Limit) internally. The Endpoint also supports the
Unlock and Type 1 Messages. The Root Port supports Interrupt, Type 1 and error
Messages.
Vendor-defined Type 0 Message TLPs are passed to the Application Layer.
The Transaction Layer treats all other received transactions (including memory or
I/O requests that do not match a defined BAR) as Unsupported Requests. The
Transaction Layer sets the appropriate error bits and transmits a completion, if
needed. These Unsupported Requests are not made visible to the Application
Layer; the header and data is dropped.
November 2011 Altera Corporation
(2)
(Part 3 of 3)
Generated by
Endpoint
App
Layer
Hot Plug Messages
Receive
No
Receive
No
Receive
No
Receive
No
Receive
No
Receive
No
Transmit
No
2.1, this message is no longer mandatory after link training.
Core (with
Core
App Layer
input)
Yes
No
Yes
No
As per the recommendations in the
Express Base Specification Revision 2.1
Yes
No
these messages are not transmitted to the
Application Layer.
Yes
No
Yes
No
Yes
No
No
Yes
8–3
Comments
PCI
,
Cyclone V Hard IP for PCI Express
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