Uncorrectable And Correctable Error Status Bits - Altera Cyclone V User Manual

12–6

Uncorrectable and Correctable Error Status Bits

The following section is reprinted with the permission of PCI-SIG. Copyright 2010
PCI-SIGR.
Figure 12–1
the bits of this register is 0. An error status bit that is set indicates that the error
condition it represents has been detected. Software may clear the error status by
writing a 1 to the appropriate bit.
Figure 12–1. Uncorrectable Error Status Register
31
Rsvd
TLP Prefix Blocked Error Status
AtomicOp Egress Blocked Status
MC Blocked TLP Status
Uncorrectable Internal Error Status
ACS Violation Status
Unsupported Request Error Status
ECRC Error Status
Malformed TLP Status
Receiver Overflow Status
Unexpected Completion Status
Completer Abort Status
Completion Timeout Status
Flow Control Protocol Status
Poisoned TLP Status
Surprise Down Error Status
Data Link Protocol Error Status
Figure 12–2
bits of this register is 0. An error status bit that is set indicates that the error condition
it represents has been detected. Software may clear the error status by writing a 1 to
the appropriate bit.0
Figure 12–2. Correctable Error Status Register
31
Header Log Overflow Status
Corrected Internal Error Status
Advisory Non-Fatal Error Status
Replay Timer Timeout Status
REPLAY_NUM Rollover Status
Bad DLLP Status
Bad TLP Status
Receiver Error Status
Cyclone V Hard IP for PCI Express
illustrates the Uncorrectable Error Status register. The default value of all
26 25 24 23 22 21 20 19
Undefined
illustrates the Correctable Error Status register. The default value of all the
Rsvd
Uncorrectable and Correctable Error Status Bits
18 17 16 15 14 13 12 11
Rsvd
16 15 14 13 12 11 9 8 7
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Chapter 12: Error Handling
6 5 4 3 1 0
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6 5 1 0
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