Altera Cyclone V User Manual page 67

Chapter 5: IP Core Interfaces
Reset Signals
Table 5–6. Reset and Link Training Signals (Part 2 of 3)
Signal I/O
I
pin_perstn
O
serdes_pll_locked
O
fixedclk_locked
I
pld_core_ready
O
pld_clk_inuse
O
dlup
O
dlup_exit
O
ev128ns
O
ev1us
O
hotrst_exit
O
l2_exit
November 2011 Altera Corporation
Active low reset from the PCIe reset pin of the device. This reset signal is an input to the
embedded reset controller for PCI Express in Cyclone V devices. It resets the datapath and
control registers. This signal is required for CvP. Cyclone V devices have 1 or 2 instances of
the Hard IP for PCI Express. Each instance has its own pin_perst signal.
Every Cyclone V devices has 2 nPERST pins, even devices with fewer than 2 instances of the
Hard IP for PCI Express. These pins have the following locations:
nPERSTL0: bottom left Hard IP and CvP blocks
■
nPERSTL1: top left Hard IP block
■
For maximum use of the Cyclone V device, Altera recommends that you use the bottom left
Hard IP first. This is the only location that supports CvP over a PCIe link.
Refer to the appropriate Cyclone V device pinout for correct pin assignment for more
detailed information about these pins. The
2.0 specifies this pin to require 3.3 V. You can drive this 3.3V signal to the pin_perst pin
even if the V of the bank is not 3.3V if the following 2 conditions are met:
CCIO
The input signal meets the V
■
■
The input signal meets the overshoot specification for 100
■
"Maximum Allowed Overshoot and Undershoot Voltage" section in the Device
for Cyclone V Devices in volume 1 of the Cyclone Device Handbook.
Refer to Figure 5–14 on page 5–17
When asserted, indicates that the PLL that generates the coreclkout_hip clock signal is
locked. In pipe simulation mode this signal is always asserted.
When asserted, indicates that the PLL that provides the fixed clock required for transceiver
initialization is locked. The Application Layer should be held in reset until fixedclk_locked
is asserted.
When asserted, indicates that the Application Layer is ready for operation and is providing a
stable clock to the pld_clk input. If the coreclkout_hip clock is the direct input to the
pld_clk input, this input can be connected to the serdes_pll_locked output. If a
different clock drives pld_clk, the corresponding lock signal for that clock should be used
to drive this input.
When asserted, indicates that the Hard IP Transaction Layer is using the pld_clk as its
clock and is ready for operation with the Application Layer. For reliable operation, hold the
Application Layer in reset until pld_clk_inuse is asserted.
When asserted, indicates that the Hard IP block is in the DLCSM DLUP state.
This signal is active for one pld_clk cycle when the IP core exits the DLCSM DLUP state.
This signal should cause the Application Layer to assert a global reset. This signal is active
low and otherwise remains high.
Asserted every 128 ns to create a time base aligned activity.
Asserted every 1 µs to create a time base aligned activity.
Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset
state. This signal should cause the Application Layer to assert a global reset. This signal is
active low and otherwise remains high.
L2 exit. This signal is active low and otherwise remains high. It is asserted for one cycle
(changing value from 1 to 0 and back to 1) after the LTSSM transitions from l2_idl to detect.
Description
PCI Express Card Electromechanical Specification
and V specification for LVTTL.
IH IL
for a timing diagram illustrating the use of this signal.
°
C operation as specified by the
Datasheet
Cyclone V Hard IP for PCI Express
User Guide
5–15