Altera Nios II Cyclone Edition Reference Manual
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Altera Nios II Cyclone Edition Reference Manual

Altera Nios II Cyclone Edition Reference Manual

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Nios Development Board
Reference Manual, Cyclone Edition
Preliminary Information
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com

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Summary of Contents for Altera Nios II Cyclone Edition

  • Page 1 Nios Development Board Reference Manual, Cyclone Edition Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com...
  • Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.

  • Page 3: About This Manual

    Bookmarks serve as an additional table of contents. ■ Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. ■ Numerous links, shown in green text, allow you to jump to related information. Altera Corporation...

  • Page 4: How To Contact Altera

    (7:30 a.m. to 5:30 p.m. Pacific Time) FTP site ftp.altera.com ftp.altera.com Note to table: You can also contact your local Altera sales office or sales representative. Typographic This document uses the typographic conventions shown below. Conventions Visual Cue Meaning...
  • Page 5 The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation...
  • Page 6 Typographic Conventions Nios Development Board Reference Manual, Cyclone Edition Altera Corporation...

  • Page 7: Table Of Contents

    Contents About this Manual ................. iii How to Find Information ........................iii How to Contact Altera ..........................iii Typographic Conventions ........................iv Board Components ................. 1 Features ..............................1–1 General Description ..........................1–1 Block Diagram ..........................1–2 Default Reference Design ........................ 1–2 Restoring the Default Reference Design to the Board ..............
  • Page 8 Connecting the Ethernet Cable ......................C–1 Connecting the LCD Screen ........................ C–2 Obtaining an IP Address ........................C–2 LAN Connection ..........................C–2 Point–to–Point Connections ......................C–4 Browsing Your Board ........................... C–5 Index viii Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 9: Board Components

    Four push-button switches connected to Cyclone user I/O pins ■ Eight LEDs connected to Straix user I/O pins ■ Dual 7-segment LED display ■ JTAG connectors to Altera devices via Altera download cables ■ 50 MHz Oscillator and zero-skew clock distribution circuitry ■ Power-on reset circuitry General...

  • Page 10: Block Diagram

    Ethernet port. For further information on the default reference design, see Appendix C, Connecting to the Board via Ethernet. 1–2 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 11: Restoring The Default Reference Design To The Board

    Restoring the Default Reference Design to the Board In the course of development, you may overwrite or erase the flash memory space containing the default reference design. Altera provides the flash image for the default reference design, so you can return the board to its default state.

  • Page 12: The Cyclone Ep1C20 Device

    Cyclone device features. EP1C20 Device Table 1–1. Cyclone EP1C20 Device Features Logic Elements 20,060 M4K RAM blocks (128 X 36 bits) Total RAM bits 294,912 PLLs Maximum user I/O pins 1–4 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 13: Flash Memory Device

    Cyclone device: Using the Quartus II software running on a host computer, a designer configures the device directly via an Altera download cable connected to the Cyclone JTAG header (J24). When power is applied to the board, a configuration controller device (U3) attempts to configure the Cyclone device with hardware configuration data stored in flash memory.

  • Page 14: Compactflash Connector

    The CompactFlash connector shares several Cyclone I/O pins with expansion prototype connector PROTO1. See “Expansion Prototype Connector (PROTO1)” on page 1–11 for details on PROTO1. Table 1–2 on page 1–7 provides CompactFlash pin out details. 1–6 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...
  • Page 15 Board Components Table 1–2. CompactFlash (CON3) Pin Table Pin on CompactFlash CompactFlash Connects to Function (CON3) -CD2 -CD1 -CE2 Altera Corporation 1–7 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 16: Sdram Device

    The SDRAM device (U57) is a Micron MT48LC4M32B2 chip with PC100 functionality and self refresh mode. The SDRAM is fully synchronous with all signals registered on the positive edge of the system clock. 1–8 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...
  • Page 17 SDRAM device as a large, linearly-addressable memory. Table 1–3. SDRAM (U57) Pin Table (Part 1 of 2) Pin Name Pin Number Connects to Cyclone Pin DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Altera Corporation 1–9 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 18: Dual Sram Devices

    They are connected to the Cyclone device so they can be used by a Nios II Devices embedded processor as general-purpose memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. 1–10 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 19: Ethernet Mac/Phy

    (for example) as an interface to a special-function daughter card. See the Altera web site for a list of available expansion daughter cards that can be used with the Nios development board at www.altera.com/devkits.
  • Page 20 Figure 1–7 show connections from the PROTO1 expansion headers to the Cyclone device. Unless otherwise noted, labels indicate Cyclone device pin numbers. Figure 1–5. Expansion Prototype Connector - J11 1–12 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 21: Expansion Prototype Connector (Proto2)

    A buffered, zero-skew copy of the on-board OSC output (from U2). ■ A buffered, zero-skew copy of the Cyclone's phase-locked loop (PLL)-output (from U60) ■ A logic-negative power-on-reset signal Altera Corporation 1–13 December 2004 Nios Development Board Reference Manual, Cyclone Edition...
  • Page 22 Figure 1–10 show connections from the PROTO2 expansion headers to the Cyclone device. Unless otherwise noted, labels indicate Cyclone device pin numbers. Figure 1–8. Expansion Prototype Connector - J16 1–14 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 23: Mictor Connector

    Mictor cable. External scopes and logic analyzers can connect to J25 and analyze a large number of signals simultaneously. For details on Nios II debugging products that use the Mictor connector, see www.altera.com. Altera Corporation 1–15 December 2004...
  • Page 24 Mictor connector to the Cyclone device. Figure 1–13 shows the pin out for J25. Unless otherwise noted, labels indicate Cyclone device pin numbers. Figure 1–12. Mictor Connector Signaling 1–16 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 25: Serial Port Connectors

    TXD. LEDs are connected to the RXD and TXD signals, giving a visual indication when data is being transmitted or received. Figure 1–14 Figure 1–15 show the pin connections between the Console and Debug serial connectors and the Cyclone device. Altera Corporation 1–17 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 26: Dual 7-Segment Display

    0, the corresponding LED turns on. See Figure 1–16 Cyclone device pin-out details. Figure 1–16. Dual-7-Segment Display The factory-programmed Nios II reference design includes parallel input/output (PIO) registers and logic for driving this display. 1–18 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 27: Push-Button Switches

    Nios II development kit. The reference designs allow the designer to access data from the EPCS4 device without using this connector. See “Cyclone Configuration” on page 1–21. Altera Corporation 1–19 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 28: Serial Configuration Device (Epcs4)

    FPGA configuration data (a .pof file) into the EPCS4 device connected to connector J28. J28 connects to the pins of U59, enabling you to program the device via an Altera download cable, such as the USB Blaster cable. The orientation of J28 is the reverse of J24. When the Altera download cable is connected to J28 correctly, the cable will rest over the Cyclone device.

  • Page 29: Reset Distribution

    Cyclone FPGA into passive serial mode and attempts to load the user configuration from flash memory. If this also fails, the configuration controller attempts to load the safe configuration in flash memory. Altera Corporation 1–21 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 30: Configuration Data

    EPM7128_PS_ config folder of the examples directory for this board. See the MAX 7000 family literature at www.altera.com/literature/lit- m7k.html for detailed information about the Altera EPM7128AE device. Configuration Data FPGA configuration data files are generated by the Quartus II software.
  • Page 31 0x600000. This data, and suitable control signals, are used in an attempt to configure the FGPA. FPGA configuration data written into this region of flash memory is conventionally called the user Altera Corporation 1–23 December 2004 Nios Development Board Reference Manual, Cyclone Edition...
  • Page 32 Do Not Erase your safe hardware image (safe hardware configuration data). If you do so inadvertently, see “Restoring the Factory Configuration” on page B–1 for instructions on how to restore your board to its factory configuration. 1–24 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 33: The Configuration-Status Leds

    LEDs (see Table 1–8). If a new configuration was downloaded into the Cyclone device via JTAG, then all of the LEDs will turn off. Altera Corporation 1–25 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 34: Configuration & Reset Buttons

    The pre-loaded Nios II reference design treats SW8 as a CPU-reset pin (see Figure 1–19). The Nios II reference design will reset and start executing code from its reset address when SW8 is pressed. 1–26 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 35: Power-Supply Circuitry

    “Power-Supply Circuitry” on page 1–28 for more details. After SW10 is pressed, the configuration controller will load the Cyclone device from flash memory. Figure 1–20. Power-On Reset Configuration Button Altera Corporation 1–27 December 2004 Nios Development Board Reference Manual, Cyclone Edition...

  • Page 36: Power-Supply Circuitry

    Figure 1–21: An external clock can be enabled by stuffing location R15 with a 49.9 ohm 0603 resistor and stuffing location R13 with a 330 ohm 0603 resistor. 1–28 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 37: Jtag Connectors

    The Nios development board, has three 10-pin JTAG headers (J24, J5 and J28) compatible with Altera download cables such as the USB Blaster Each JTAG header connects to one Altera device and forms a single- device JTAG chain. J24 connects to the Cyclone device (U60), J5 connects into the EPM7128AE device (U3), and J28 connects to the EPCS4 serial- configuration device (U59).

  • Page 38: Jtag Connector To Epm7128Ae Device (J5)

    J5 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the EMP7128AE device (U3) as shown in Figure 1–24. Altera Quartus II software can perform in-system programming (ISP) to reprogram the EMP7128AE device (U3) with a new hardware configuration via an Altera download cable.
  • Page 39 Board Components Figure 1–24. JTAG Connector (J5) to EPM7128AE Device Pin 1 Altera Corporation 1–31 December 2004 Nios Development Board Reference Manual, Cyclone Edition...
  • Page 40 JTAG Connectors 1–32 Altera Corporation Nios Development Board Reference Manual, Cyclone Edition December 2004...

  • Page 41: Appendix A. Shared Bus Table

    Pin # Pin # Pin # Name Name Name Name Name FSE_A0 Shared Address FSE_A1 FSE_A2 FSE_A3 FSE_A4 FSE_A5 FSE_A6 FSE_A7 FSE_A8 FSE_A9 FSE_A10 FSE_A11 FSE_A12 FSE_A13 FSE_A14 FSE_A15 FSE_A16 FSE_A17 FSE_A18 FSE_A19 FSE_A20 FSE_A21 FSE_A22 Altera Corporation A–1 December 2004...
  • Page 42 Name FSE_D0 Shared Data FSE_D1 FSE_D2 FSE_D3 FSE_D4 FSE_D5 FSE_D6 FSE_D7 FSE_D8 FSE_D9 FSE_D10 FSE_D11 FSE_D12 FSE_D13 FSE_D14 FSE_D15 FSE_D16 FSE_D17 FSE_D18 FSE_D19 FSE_D20 FSE_D21 FSE_D22 FSE_D23 FSE_D24 FSE_D25 FSE_D26 FSE_D27 FSE_D28 FSE_D29 FSE_D30 FSE_D31 A–2 Altera Corporation December 2004...
  • Page 43 CYCLE ENET_DATACS_N Data Chip DATAC Select ENET_INTRQ0 Interrupt INTRO ENET_IOCHRDY IO Char ARDY Ready ENET_IOR_N Read ENET_IOW_N Write ENET_LCLK Local Bus LCLK Clock ENET_LDEV_N Local Device LDEV# ENET_RDYRTN_N Ready Return IO RDYRT ENET_W_R_N Write/Read W/R# Altera Corporation A–3 December 2004...

  • Page 44: Description

    Description A–4 Altera Corporation December 2004...

  • Page 45: Appendix B. Restoring The Factory Configuration

    Flash Open a Nios II SDK Shell by choosing Windows Start > Programs > Memory Altera > Nios II Development Kit <installed version> > Nios II SDK Shell. From the example directory, change to the factory_recovery directory for your development kit.

  • Page 46: Reprogramming The Epm7128Ae Configuration Controller Device

    Push the Force Safe button to perform a power-on reset and reconfigure the Cyclone device from Flash memory. You should see the Safe LED turned on and activity on LEDs D0 through D7. Your board is now re-configured to the default factory condition. B–2 Altera Corporation December 2004...

  • Page 47: Appendix C. Connecting To The Board Via Ethernet

    Insert the male end of the crossover adapter into RJ1 on the Nios development board. Connect the other end of the RJ45 connector directly to the network (Ethernet) port on your host computer (see Figure C–1 on page C–2). Altera Corporation C–1 December 2004...

  • Page 48: Connecting The Lcd Screen

    Connecting the LCD Screen Figure C–1. Point-to-Point Connection Connecting the Your Nios II development kit was delivered with a two-line x 16- character LCD text screen. The web-server software displays useful status LCD Screen and progress messages on this display. If you wish to use the network features of the board, connect the LCD screen to the Expansion Prototype Connector (J12), as shown in Figure...
  • Page 49 Once you know a safe IP address, you can assign it to your board using the steps below. These steps send IP configuration data to the board via an Altera JTAG download cable, such as the USB Blaster cable.

  • Page 50: Point-To-Point Connections

    Obtaining an IP Address The monitor's prompt is the + character. You can enter h<Enter> at the prompt for a complete list of supported commands. At the prompt, type xip:<safe IP address><Enter> The xip command saves the IP address in flash memory. In general, you will only need to assign an IP address to your board once.

  • Page 51: Browsing Your Board

    URL directly into the browser’s Address input field. You can determine your board’s IP address by reading the messages displayed on the LCD screen (the IP address is continuously displayed). Altera Corporation C–5 December 2004...
  • Page 52 Browsing Your Board C–6 December 2004...
  • Page 53 JTAG to MAX device (J5) 1–30 Indicators 1–26 JTAG connectors 1–29 Conventional flash memory usage 1–23 Cyclone EP1C20 device 1–4 Mictor connector 1–15 Debug port to OCI debug module 1–16 Development board J25 pin information 1–17 Features 1–1 Altera Corporation Index–1 December 2004...
  • Page 54 J27 pin information 1–18 Restore factory configuration Shared bus table A–1 Reprogramming the EPM7128AE configura- SRAM devices 1–10 tion controller device B–2 SW10 button 1–27 Reprogramming the flash memory B–1 SW8 button 1–26 SW9 button 1–27 Index–2 Altera Corporation December 2004...

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