Altera Cyclone V User Manual page 87

Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Table 5–22. PIPE Interface Signals (Part 3 of 3)
Signal
ltssmstate0[4:0]
sim_pipe_rate
sim_pipe_pclk_in
Notes to Table 5–22:
(1) Signals that include lane number 0 also exist for lanes 1-7.
(2) These signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating.
November 2011 Altera Corporation
I/O
LTSSM state: The LTSSM state machine encoding defines the following
states:
00000: detect.quiet
■
00001: detect.active
■
00010: polling.active
■
00011: polling.compliance
■
00100: polling.configuration
■
00101: polling.speed
■
00110: config.linkwidthstart
■
00111: config.linkaccept
■
01000: config.lanenumaccept
■
01001: config.lanenumwait
■
01010: config.complete
■
01011: config.idle
O ■
01100: recovery.rcvlock
■
01101: recovery.rcvconfig
■
01110: recovery.idle
■
01111: L0
■
10000: disable
■
10001: loopback.entry
■
10010: loopback.active
■
10011: loopback.exit
■
10100: hot.reset
■
10101: LOs
■
11001: L2.transmit.wake
■
11010: speed.recovery
■
Specifies the lane rate. The 2-bit encodings have the following
meanings:
2'b00–reserved
■
O
2'b01: Gen1 rate (2.5 Gbps)
■
2'b10: Gen2 rate (5.0 Gbps)
■
2'b11–Gen3 rate (8.0 Gbps)
■
This clock is used for PIPE simulation only, and is derived from the
I
refclk. It is the PIPE interface clock used for PIPE mode simulation.
Description
Cyclone V Hard IP for PCI Express
5–35
User Guide