Altera Cyclone V User Manual page 53

November 2011
1101
This chapter describes the signals that are part of the Cyclone V Hard IP for PCI
Express IP core.
Because the Cyclone V Hard IP for PCI Express offers exactly the same feature set in
the MegaWizard Plug-In Manager and Qsys design flows, your decision about which
design flow to use depends on whether you want to integrate the Cyclone V Hard IP
for PCI Express using RTL instantiation or Qsys. The Qsys system integration tool
automatically generates the interconnect logic between the IP components in your
system, saving time and effort. Refer to
on page 2–3
involved in the two design flows.
Table 5–1
describe each signal. The signals are described in the order in which they are shown in
Figure
Table 5–1. Signal Groups in the Cyclone V Hard IP for PCI Express
Signal Group
Avalon-ST RX
Avalon-ST TX
Clock
Reset and link training
ECC error
Interrupt
Interrupt and global error
Configuration space
LMI
Completion
Power management
Transceiver control
Serial
(1)
PIPE
Test
Note to Table 5–1:
(1) Provided for simulation only
November 2011 Altera Corporation
Figure 5–1 on page 5–2
and "Qsys Design Flow" on page 2–9
lists each interface and provides a link to the subsequent sections that
5–1.
Logical
"Avalon-ST RX Interface" on page 5–3
"Avalon-ST TX Interface" on page 5–8
"Clock Signals" on page 5–14
"Reset Signals" on page 5–14
"ECC Error Signals" on page 5–17
"Interrupts for Endpoints" on page 5–17
"Interrupts for Root Ports" on page 5–18
"Transaction Layer Configuration Space Signals" on page 5–20
"LMI Signals" on page 5–27
"Completion Side Band Signals" on page 5–19
"Power Management Signals" on page 5–30
Physical
"Transceiver Reconfiguration" on page 5–32
"Serial Interface Signals" on page 5–32
"PIPE Interface Signals" on page 5–33
Test
"Test Signals" on page 5–36
5. IP Core Interfaces
illustrates the top-level signals IP core.
"MegaWizard Plug-In Manager Design Flow"
for a description of the steps
Description
Cyclone V Hard IP for PCI Express