Altera Cyclone V User Manual page 27

Chapter 2: Getting Started
Qsys Design Flow
f
For more information about Avalon interfaces, refer to the
Specifications.
3. Connect the following Avalon Conduit interfaces using the technique described in
Step 1.
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4. Follow these steps to connect the clocks:
a. In the Clock column right-click on the DUT pld_clk interface and select
b. To connect the APPS pld_clk_hip interface to the DUT pld_clk interface,
c. To connect the DUT coreclkout_hip interface to the APPS coreclkout_hip
d. To connect the DUT coreclkout_hip interface to the APPS coreclkout_hip
5. To remove the default clock, on the System Contents tab, click clk_0 and then click
the
6. To save your Qsys system, on the File menu select Save. Type pcie_qsys in the
Save dialog box.
November 2011 Altera Corporation
lmi
config_tl
power_mgmt
hip_status
rx_bar_be
tx_cred
hip_rst
reconfig_to_xcvr
reconfig_from_xcvr
int_msi
APPS.pld_clk_hip from the DUT.pld_clk Connections list.
right-click on APPS.pld_clk_hip and select DUT.pld_clk from the
APPS.pld_clk_hip Connections list.
interface, right-click on DUT.coreclkout_hip and select DUT.coreclkout_hip
from the DUT.coreclkout_hip Connections list. CHECK
interface, right-click on DUT.coreclkout_hip and select APPS.coreclkout_hip
from the DUT.coreclkout_hip Connections list.
X button.
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Avalon Interface
Cyclone V Hard IP for PCI Express
User Guide