Altera Cyclone V User Manual page 109
Hard ip for pci express
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Also See for Cyclone V:
- Technical reference (3536 pages) ,
- Device handbook (1077 pages) ,
- Reference manual (66 pages)
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Chapter 9: Optional Features
Lane Initialization and Reversal
The Cyclone V Hard IP for PCI Express supports lane reversal, which permits the
logical reversal of lane numbers for the ×1, ×2, and ×4. Lane reversal allows more
flexibility in board layout, reducing the number of signals that must cross over each
other when routing the PCB.
Table 9–3
Table 9–3. Lane Assignments without Lane Reversal
Lane Number
×4 IP core
×1 IP core
Table 9–4
Table 9–4. Lane Assignments with Lane Reversal
Core Config
Lane
assignments
Figure 9–1
the top side of the PCB. Connecting the lanes without lane reversal creates routing
problems. Using lane reversal, solves the problem.
Figure 9–1. Using Lane Reversal to Solve PCB Routing Problems
No Lane Reversal
Results in PCB Routing Challenge
Root Port
November 2011 Altera Corporation
summarizes the lane assignments for normal configuration.
summarizes the lane assignments with lane reversal.
4
Slot Size
8
7:0,6:1,5:2,4:3
illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoint on
Endpoint
0
3
1
2
no lane
2
1
reversal
3
0
3
2
3
2
—
—
4
2
3:0,2:1,1:2,0:3
3:0,2:1
With Lane Reversal
Signals Route Easily
Root Port
0
0
1
1
2
2
3
3
1
0
1
0
—
0
1
1
8
4
2
3:0
7:0
3:0
1:0
0:0
Endpoint
lane
reversal
Cyclone V Hard IP for PCI Express
User Guide
9–3
1
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