Clocks - Altera Cyclone V User Manual

7–2
■ npor and pin_perst—These signals reset all sticky registers that may not be reset
in L2 low power mode or by the fundamental reset.
srst—The srst signal initiates a synchronous reset of the datapath state
■
machines.
crst—The crst signal initiates a synchronous reset of the nonsticky Configuration
■
Space registers.
1
The Cyclone V embedded reset sequence meets the 100 ms configuration time
specified in the

Clocks

In accordance with the
reference clock that is connected directly to the transceiver. As a convenience, you
may also use a 125 MHz input reference clock as input to the TX PLL. The output of
the transceiver drives coreclkout_hip. coreclkout_hip must be connected back to
the pld_clk input clock, possibly through a clock distribution circuit required by the
specific application.
The Hard IP contains a clock domain crossing (CDC) synchronizer at the interface
between the PHY/MAC and the DLL layers which allows the Data Link and
Transaction Layers to run at frequencies independent of the PHY/MAC and provides
more flexibility for the user clock interface. Depending on system requirements, you
can use this additional flexibility to enhance performance by running at a higher
frequency for latency optimization or at a lower frequency to save power.
Figure 7–2
Figure 7–2. Cyclone V Hard IP for PCI Express Clock Domains
PCS
Transceiver
250 or 500 MHz
TX PLL
refclk
100 MHz
(or 125 MHz)
Cyclone V Hard IP for PCI Express
PCI Express Base Specification 2.1.
PCI Express Base Specification
illustrates the clock domains.
Hard IP for PCI Express
Clock
Domain
PHY/MAC
Crossing
(CDC)
p_clk
Chapter 7: Reset and Clocks
2.1, you must provide a 100 MHz
Data Link
and
Transaction
pld_clk (250 MHz)
Layers
pld_clk (125 MHz)
coreclk
coreclkout_hip
November 2011 Altera Corporation
Clocks
Application
Layer
PLL