Altera Cyclone V User Manual page 105

Chapter 8: Transaction Layer Protocol (TLP) Details
Receive Buffer Reordering
Table 8–2. Transaction Ordering Rules
Read Request
I/O or
Configuration
Write Request
N
Read Completion
Y/N
I/O or
Configuration
Y/N
Write
Completion
Notes to Table 8–2:
(1) A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b'0) must not pass any other Memory Write or Message
Request.
(2) A Memory Write or Message Request with the Relaxed Ordering Attribute bit set (b'1) is permitted to pass any other Memory Write or Message
Request.
(3) Endpoints, Switches, and Root Complex may allow Memory Write and Message Requests to pass Completions or be blocked by Completions.
(4) Memory Write and Message Requests can pass Completions traveling in the PCI Express to PCI directions to avoid deadlock.
(5) If the Relaxed Ordering attribute is not set, then a Read Completion cannot pass a previously enqueued Memory Write or Message Request.
(6) If the Relaxed Ordering attribute is set, then a Read Completion is permitted to pass a previously enqueued Memory Write or Message Request.
(7) Read Completion associated with different Read Requests are allowed to be blocked by or to pass each other.
(8) Read Completions for Request (same Transaction ID) must return in address order.
(9) Non-posted requests cannot pass other non-posted requests.
(10) Refers to the PCI Express Base Specification 3.0.
(11) CfgRd0 can pass IORd or MRd.
(12) CfgWr0 can IORd or MRd.
(13) CfgRd0 can pass IORd or MRd.
(14) CfrWr0 can pass IOWr.
1
MSI requests are conveyed in exactly the same manner as PCI Express memory write
requests and are indistinguishable from them in terms of flow control, ordering, and
data integrity.
November 2011 Altera Corporation
(1)– (9)
(Part 2 of 2)
N N Y/N N
N N Y/N N
(11) (11)
N
Y
(12) (12)
N
N Y
(11) (12)
Y/N N
(13) (14)
Y/N N
Y/N
Y Y Y
N
Y Y Y
Y/N N Y/N
Y/N N Y/N
(11) (11)
N
Y/N
(12) (12)
N
Y/N N Y/N
Cyclone V Hard IP for PCI Express
User Guide
8–5
N
N
N
N