Altera Cyclone V User Manual page 73

Chapter 5: IP Core Interfaces
Transaction Layer Configuration Space Signals
Table 5–11. Configuration Space Signals (Hard IP Implementation) (Part 2 of 2)
Signal Width Dir Description
123
tl_cfg_sts
1
tl_cfg_sts_wr
5
[0]
[1]
hpg_ctrler
[2]
[3]
[4]
November 2011 Altera Corporation
Configuration status bits. This information updates every pld_clk cycle. Bits[52:0]
record status information for function0. Bits[62:53] record information for function1.
0
Bits[72:63] record information for function 2, and so on. Refer to
detailed description of the status bits.
Write signal. This signal toggles when tl_cfg_sts has been updated (every 8
0 core_clk cycles). The toggle marks the edge where tl_cfg_sts data changes. You
can use this edge as a reference to determine when the data is safe to sample.
The hpg_ctrler signals are only available in Root Port mode and when the
Capability register is enabled. Refer to the
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page 3–6. For Endpoint variations the hpg_ctrler input should be hardwired to 0s.
The bits have the following meanings:
Attention button pressed. This signal should be asserted when the attention button is
pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and
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the Attention Button Present bit (bit[0]) in the
should be set to 0.
Presence detect. This signal should be asserted when a presence detect circuit detects
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a presence change in the slot.
Manually-operated retention latch (MRL) sensor changed. This signal should be
asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does
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not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor Present
bit (bit[2]) in the Slot Capability register
Power fault detected. This signal should be asserted when the power controller detects
a power fault for this slot. If this slot has no power controller, this bit should be
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hardwired to 0, and the Power Controller Present bit (bit[1]) in the
register parameter should be set to 0.
Power controller status. This signal is used to set the command completed bit of the
Slot Status register. Power controller status is equal to the power controller control
I signal. If this slot has no power controller, this bit should be hardwired to 0 and the
Power Controller Present bit (bit[1]) in the
disabled.
Table 5–12
Use Slot register parameter in
Slot Capability registerparameter
parameter should be set to 0.
Slot Capability register
Cyclone V Hard IP for PCI Express
5–21
for a
Slot
Table 3–5 on
Slot Capability
should be
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