Altera Stratix IV Manuals

Manuals and User Guides for Altera Stratix IV. We have 3 Altera Stratix IV manuals available for free PDF download: Device Handbook, Handbook, Using Manual

Altera Stratix IV Device Handbook (1157 pages)

Brand: Altera | Category: Motherboard | Size: 33.02 MB

Table of Contents

3
- Volume
  11
- Feature Summary
  16
  - Stratix IV GX Devices
    17
  - Stratix IV E Device
    18
  - Stratix IV GT Devices
    19
- Architecture Features
  20
  - Diagnostic Features
    21
  - FPGA Fabric and I/O Features
    22
- Plls
  23
  - System Integration
    24
- Integrated Software Platform
  33
- Logic Array Blocks
  37
  - LAB Interconnects
    40
- Adaptive Logic Modules
  41
  - ALM Operating Modes
    44
    
    Normal Mode
    45
    
    Extended LUT Mode
    47
    
    Arithmetic Mode
    48
    
    Shared Arithmetic Mode
    50
    
    LUT-Register Mode
    51
  - Register Chain
    53
  - ALM Interconnects
    54
  - LAB Power Management Techniques
    55
  - Overview
    57
  - Trimatrix Memory Block Types
    59
  - Packed Mode Support
    61
  - Address Clock Enable Support
    62
  - Mixed Width Support
    63
  - Error Correction Code (ECC) Support
    64
- Memory Modes
  65
  - Single-Port RAM Mode
    66
  - Simple Dual-Port Mode
    67
  - True Dual-Port Mode
    70
  - Shift-Register Mode
    72
  - ROM Mode
    73
  - Independent Clock Mode
    74
  - Conflict Resolution
    75
    
    Mixed-Port Read-During-Write Mode
    77
  - Power-Up Conditions and Memory Initialization
    79
  - Power Management
    80
- Chapter 4 .DSP Blocks in Stratix IV Devices
  
  82
  - Stratix IV DSP Block Overview
    82
  - Stratix IV Simplified DSP Operation
    84
  - Stratix IV Operational Modes Overview
    88
  - Stratix IV DSP Block Resource Descriptions
    89
    
    Input Registers
    90
    
    Multiplier and First-Stage Adder
    92
    
    Pipeline Register Stage
    93
    
    Rounding and Saturation Stage
    94
  - Stratix IV Operational Mode Descriptions
    95
    
    Bit Multiplier
    99
    
    Double Multiplier
    100
    
    Two-Multiplier Adder Sum Mode
    102
    
    X 18 Complex Multiply
    104
    
    Four-Multiplier Adder
    106
    
    High-Precision Multiplier Adder Mode
    107
    
    Multiply Accumulate Mode
    109
    
    Shift Modes
    110
    
    Rounding and Saturation Mode
    112
    
    DSP Block Control Signals
    114
    
    Software Support
    115
    
    Software Support
    116
- Chapter 5 .Clock Networks and Plls in Stratix IV Devices
  
  119
  - Clock Networks in Stratix IV Devices
    119
    
    Global Clock Networks
    121
    
    Regional Clock Networks
    122
    
    Periphery Clock Networks
    124
    
    Clock Sources Per Quadrant
    127
    
    Clock Network Sources
    128
    
    PLL Clock Outputs
    129
    
    Clock Input Connections to the Plls
    130
    
    Clock Output Connections
    131
    
    Clock Control Block
    132
    
    Clock Enable Signals
    135
    
    Clock Source Control for Plls
    136
    
    Cascading Plls
    137
    
    Stratix IV PLL Hardware Overview
    141
    
    PLL Clock I/O Pins
    142
    
    PLL Control Signals
    145
    
    Clock Feedback Modes
    146
    
    Source Synchronous Mode
    147
    
    Source-Synchronous Mode for LVDS Compensation
    148
    
    Normal Mode
    149
    
    External Feedback Mode
    150
    
    Clock Multiplication and Division
    151
    
    Post-Scale Counter Cascading
    152
    
    Programmable Duty Cycle
    153
    
    Programmable Bandwidth
    155
    
    Implementation
    156
    
    Spread-Spectrum Tracking
    157
    
    Automatic Clock Switchover
    158
    
    Manual Clock Switchover
    161
    
    PLL Reconfiguration
    162
    
    PLL Reconfiguration Hardware Implementation
    163
    
    Post-Scale Counters (C0 to C9)
    165
    
    Scan Chain Description
    166
    
    Charge Pump and Loop Filter
    168
    
    Bypassing a PLL
    169
    
    PLL Specifications
    172
- Chapter 6 .I/O Features in Stratix IV Devices
  
  178
  - I/O Standards Support
    178
    
    I/O Standards and Voltage Levels
    179
  - I/O Banks
    181
    
    Modular I/O Banks
    184
  - I/O Structure
    193
    
    V I/O Interface
    195
    
    High-Speed Differential I/O with DPA Support
    196
    
    Programmable Slew Rate Control
    197
    
    Programmable I/O Delay
    198
    
    Programmable Pull-Up Resistor
    199
  - On-Chip Termination Support and I/O Termination Schemes
    200
    
    On-Chip Series Termination with Calibration
    202
    
    Left-Shift Series Termination Control
    203
    
    On-Chip Parallel Termination with Calibration
    204
    
    Expanded On-Chip Series Termination with Calibration
    205
    
    Summary of OCT Assignments
    207
    
    OCT Calibration
    208
    
    Sharing an OCT Calibration Block on Multiple I/O Banks
    210
    
    OCT Calibration Block Modes of Operation
    211
  - User Mode
    212
  - OCT Calibration
    213
    
    Example of Using Multiple OCT Calibration Blocks
    214
    
    Differential I/O Standards Termination
    217
    
    Lvds
    219
    
    Differential LVPECL
    220
    
    Rsds
    221
    
    Mini-LVDS
    222
    
    Non-Voltage-Referenced Standards
    223
  - Memory Interfaces Pin Support
    229
    
    Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
    252
    
    Rules to Combine Groups
    253
  - Stratix IV External Memory Interface Features
    255
    
    Phase Offset Control
    267
    
    DQS Logic Block
    269
    
    DQS Delay Chain
    270
    
    DQS Postamble Circuitry
    271
    
    Leveling Circuitry
    272
    
    Dynamic On-Chip Termination Control
    274
    
    I/O Element Registers
    275
    
    Delay Chain
    278
    
    I/O Configuration Block and DQS Configuration Block
    280
- Chapter 13 .Power Management in Stratix IV Devices
  
  283
  - Overview
    283
- Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
  
  285
  - Locations of the I/O Banks
    285
  - LVDS Channels
    286
  - Lvds Serdes
    290
  - ALTLVDS Port List
    291
  - Differential Transmitter
    293
    
    Programmable VOD
    297
    
    Programmable Pre-Emphasis
    298
  - Differential Receiver
    299
    
    Differential I/O Termination
    300
    
    Receiver Hardware Blocks
    301
    
    Synchronizer
    302
    
    Deserializer
    304
    
    DPA Mode
    306
    
    Soft-CDR Mode
    307
  - LVDS Interface with the Use External PLL Option Enabled
    308
  - Left and Right Plls (Pll_Lx and Pll_Rx)
    311
  - Stratix IV Clocking
    312
  - Source-Synchronous Timing Budget
    313
    
    Transmitter Channel-To-Channel Skew
    315
  - Differential Pin Placement Guidelines
    320
    
    Using both Center Left and Right Plls
    322
    
    Guidelines for DPA-Disabled Differential Channels
    324
    
    Using both Center Left and Right Plls
    327
- Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices
  
  333
- Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
  
  340
  - Configuration Devices
    340
  - Configuration Features
    342
  - Power-On Reset Circuit
    343
  - Fast Passive Parallel Configuration
    344
    
    FPP Configuration Timing
    350
    
    FPP Configuration Using a Microprocessor
    354
    
    VCCPGM Pins
    355
    
    Estimating Active Serial Configuration Time
    360
    
    Programming Serial Configuration Devices
    361
    
    Guidelines for Connecting Serial Configuration Devices on an as Interface
    363
    
    PS Configuration Using a MAX II Device as an External Host
    364
    
    PS Configuration Timing
    369
    
    PS Configuration Using a Microprocessor
    370
  - JTAG Configuration
    373
    
    Jam STAPL
    378
  - Configuration Data Decompression
    386
  - Remote System Upgrades
    388
    
    Functional Description
    389
    
    Enabling Remote Update
    391
    
    Configuration Image Types
    392
  - Dedicated Remote System Upgrade Circuitry
    395
    
    Remote System Upgrade Registers
    396
    
    Remote System Upgrade Status Register
    397
    
    Remote System Upgrade State Machine
    398
    
    User Watchdog Timer
    400
  - Quartus II Software Support
    401
  - Design Security
    402
    
    Stratix IV Security Protection
    403
    
    Stratix IV Design Security Solution
    404
    
    Security Modes Available
    405
    
    No Key Operation
    406
    
    VCCPD Pins
    408
- Chapter 11 .SEU Mitigation in Stratix IV Devices
  
  410
  - Error Detection Fundamentals
    410
    
    Automated Single-Event Upset Detection
    413
  - Error Detection Block
    414
    
    Error Detection Registers
    415
  - Error Detection Timing
    416
    
    Software Support
    418
  - Recovering from CRC Errors
    419
- Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices
  
  421
  - BST Architecture
    421
  - BST Operation Control
    422
  - I/O Voltage Support in a JTAG Chain
    424
    
    Overview
    427
  - Stratix IV Power Technology
    428
  - Stratix IV External Power Supply Requirements
    429
  - Temperature Sensing Diode
    430
  - About this Handbook
    433
    
    Peripheral Devices
    623
. Altgx_Reconfig Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration/Additional Information

953
- Power Supplies
  1025
- Pin-Out File
  1030
- Resource Section
  1030
- Verification
  1030
- Functional Simulation
  1031
- Guidelines to Debug Transceiver-Based Designs
  1033
  - Guidelines to Debug the FPGA Logic and the Transceiver Interface
    1033
  - Guidelines to Debug System Level Issues
    1034
- Example 1: Fibre Channel Protocol Application
  1036
- Chapter 3. ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration
  
  1060
  - Additional Information
    1074
    
    How to Contact Altera
    1074
    
    Typographic Conventions
    1074
Table of Contents

1078
- Chapter Revision Dates
  1080
- Chapter 1. DC and Switching Characteristics for Stratix IV Devices
  
  1082
  - Recommended Operating Conditions
    1088
  - DC Characteristics
    1090
  - Internal Weak Pull-Up Resistor
    1094
    
    Power Consumption
    1098
    
    Transceiver Performance Specifications
    1099
    
    Transceiver Datapath PCS Latency
    1130
    
    Core Performance Specifications
    1130
    
    Clock Tree Specifications
    1130
    
    PLL Specifications
    1131
    
    DSP Block Specifications
    1133
    
    Trimatrix Memory Block Specifications
    1134
    
    Configuration and JTAG Specifications
    1135
    
    Temperature Sensing Diode Specifications
    1136
    
    Chip-Wide Reset (Dev_Clrn) Specifications
    1137
    
    Periphery Performance
    1137
    
    High-Speed I/O Specification
    1137
    
    OCT Calibration Block Specifications
    1144
    
    Duty Cycle Distortion (DCD) Specifications
    1145
  - I/O Timing
    1145
    
    Programmable IOE Delay
    1146
    
    Programmable Output Buffer Delay
    1146
  - Glossary
    1147
  - Section I. Device Datasheet and Addendum for Stratix IV Devices
    1082
- Chapter 2. Addendum to the Stratix IV Device Handbook
  
  1154
  - Additional Information
    1156
    
    How to Contact Altera
    1156
    
    Typographic Conventions
    1156

Altera Stratix IV Handbook (434 pages)

Brand: Altera | Category: Transceiver | Size: 12.23 MB

Table of Contents
3
Chapter Revision Dates

11
- Volume
  11
Section I. Device Core

13
- Feature Summary
  16
  - Stratix IV GX Devices
    17
  - Stratix IV E Device
    18
  - Stratix IV GT Devices
    19
- Architecture Features
  20
  - High-Speed Transceiver Features
    20
    
    Highest Aggregate Data Bandwidth
    20
    
    Wide Range of Protocol Support
    20
    
    Diagnostic Features
    21
    
    Signal Integrity
    21
  - FPGA Fabric and I/O Features
    22
    
    Device Core Features
    22
    
    Embedded Memory
    22
    
    Digital Signal Processing (DSP) Blocks
    22
    
    Clock Networks
    22
    
    Plls
    23
    
    I/O Features
    23
    
    High-Speed Differential I/O with DPA and Soft-CDR
    23
    
    External Memory Interfaces
    23
    
    System Integration
    24
- Integrated Software Platform
  33
- Ordering Information
  33
Chapter 1. Overview for the Stratix IV Device Family

13
Chapter 2 .Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices

37
- Logic Array Blocks
  37
  - LAB Interconnects
    40
  - LAB Control Signals
    40
- Adaptive Logic Modules
  41
  - ALM Operating Modes
    44
    
    Normal Mode
    45
    
    Extended LUT Mode
    47
    
    Arithmetic Mode
    48
    
    Shared Arithmetic Mode
    50
    
    LUT-Register Mode
    51
  - Register Chain
    53
  - ALM Interconnects
    54
  - Clear and Preset Logic Control
    54
  - LAB Power Management Techniques
    55
Chapter 3. Trimatrix Embedded Memory Blocks in Stratix IV Devices

57
- Overview
  57
  - Trimatrix Memory Block Types
    59
  - Parity Bit Support
    59
  - Byte Enable Support
    59
  - Packed Mode Support
    61
  - Address Clock Enable Support
    62
  - Mixed Width Support
    63
  - Asynchronous Clear
    63
  - Error Correction Code (ECC) Support
    64
- Memory Modes
  65
  - Single-Port RAM Mode
    66
  - Simple Dual-Port Mode
    67
  - True Dual-Port Mode
    70
  - Shift-Register Mode
    72
  - ROM Mode
    73
  - FIFO Mode
    73
- Clocking Modes
  73
  - Independent Clock Mode
    74
  - Input/Output Clock Mode
    74
  - Read/Write Clock Mode
    74
  - Single Clock Mode
    74
- Design Considerations
  74
Chapter 4. DSP Blocks in Stratix IV Devices

82
- Stratix IV DSP Block Overview
  82
- Stratix IV Simplified DSP Operation
  84
- Stratix IV Operational Modes Overview
  88
- Stratix IV DSP Block Resource Descriptions
  89
  - Input Registers
    90
  - Multiplier and First-Stage Adder
    92
  - Pipeline Register Stage
    93
  - Second-Stage Adder
    93
  - Rounding and Saturation Stage
    94
  - Second Adder and Output Registers
    94
- Stratix IV Operational Mode Descriptions
  95
  - Independent Multiplier Modes
    95
  - 12-, and 18-Bit Multiplier
    95
  - 36-Bit Multiplier
    99
  - Double Multiplier
    100
  - Two-Multiplier Adder Sum Mode
    102
  - 18 X 18 Complex Multiply
    104
  - Four-Multiplier Adder
    106
  - High-Precision Multiplier Adder Mode
    107
  - Multiply Accumulate Mode
    109
  - Shift Modes
    110
  - Rounding and Saturation Mode
    112
  - DSP Block Control Signals
    114
- Software Support
  115
- Software Support
  116
Chapter 5 .Clock Networks and Plls in Stratix IV Devices

119
- Clock Networks in Stratix IV Devices
  119
  - Global Clock Networks
    121
  - Regional Clock Networks
    122
  - Periphery Clock Networks
    124
  - Clock Sources Per Quadrant
    127
  - Clock Regions
    127
  - Clock Network Sources
    128
    
    Dedicated Clock Input Pins
    128
    
    Labs
    128
    
    PLL Clock Outputs
    129
  - Clock Input Connections to the Plls
    130
  - Clock Output Connections
    131
  - Clock Control Block
    132
  - Clock Enable Signals
    135
  - Clock Source Control for Plls
    136
  - Cascading Plls
    137
- Plls in Stratix IV Devices
  137
  - Stratix IV PLL Hardware Overview
    141
    
    PLL Clock I/O Pins
    142
  - PLL Control Signals
    145
    
    Pfdena
    145
    
    Areset
    145
    
    Locked
    145
  - Clock Feedback Modes
    146
    
    Source Synchronous Mode
    147
    
    Source-Synchronous Mode for LVDS Compensation
    148
    
    No-Compensation Mode
    148
    
    Normal Mode
    149
    
    Zero-Delay Buffer (ZDB) Mode
    149
    
    External Feedback Mode
    150
  - Clock Multiplication and Division
    151
  - Post-Scale Counter Cascading
    152
  - Programmable Duty Cycle
    153
  - Programmable Phase Shift
    153
  - Programmable Bandwidth
    155
    
    Background
    155
    
    Implementation
    156
  - Spread-Spectrum Tracking
    157
  - Clock Switchover
    157
    
    Automatic Clock Switchover
    158
    
    Manual Clock Switchover
    161
    
    Guidelines
    161
  - PLL Reconfiguration
    162
    
    PLL Reconfiguration Hardware Implementation
    163
    
    Post-Scale Counters (C0 to C9)
    165
    
    Scan Chain Description
    166
    
    Charge Pump and Loop Filter
    168
    
    Bypassing a PLL
    169
    
    Dynamic Phase-Shifting
    169
  - PLL Specifications
    172
Chapter 6 .I/O Features in Stratix IV Devices

178
- I/O Standards Support
  178
  - I/O Standards and Voltage Levels
    179
- I/O Banks
  181
  - Modular I/O Banks
    184
- I/O Structure
  193
  - V I/O Interface
    195
  - High-Speed Differential I/O with DPA Support
    196
  - Programmable Slew Rate Control
    197
  - Programmable I/O Delay
    198
  - Programmable Pull-Up Resistor
    199
- On-Chip Termination Support and I/O Termination Schemes
  200
- OCT Calibration
  208
  - Sharing an OCT Calibration Block on Multiple I/O Banks
    210
  - OCT Calibration Block Modes of Operation
    211
- User Mode
  212
  - OCT Calibration
    213
    
    Example of Using Multiple OCT Calibration Blocks
    214
  - Differential I/O Standards Termination
    217
  - Lvds
    219
    
    Differential LVPECL
    220
    
    Rsds
    221
    
    Mini-LVDS
    222
    
    Non-Voltage-Referenced Standards
    223
- Memory Interfaces Pin Support
  229
  - Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
    252
  - Rules to Combine Groups
    253
- Stratix IV External Memory Interface Features
  255
  - Phase Offset Control
    267
  - DQS Logic Block
    269
    
    DQS Delay Chain
    270
    
    DQS Postamble Circuitry
    271
  - Leveling Circuitry
    272
  - Dynamic On-Chip Termination Control
    274
  - I/O Element Registers
    275
  - Delay Chain
    278
  - I/O Configuration Block and DQS Configuration Block
    280
  - Overview
    283
Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices

285
- Locations of the I/O Banks
  285
- LVDS Channels
  286
- Lvds Serdes
  290
- ALTLVDS Port List
  291
- Differential Transmitter
  293
  - Programmable VOD
    297
  - Programmable Pre-Emphasis
    298
- Differential Receiver
  299
  - Differential I/O Termination
    300
  - Receiver Hardware Blocks
    301
    
    Synchronizer
    302
    
    Deserializer
    304
    
    DPA Mode
    306
    
    Soft-CDR Mode
    307
- LVDS Interface with the Use External PLL Option Enabled
  308
- Left and Right Plls (Pll_Lx and Pll_Rx)
  311
- Stratix IV Clocking
  312
- Source-Synchronous Timing Budget
  313
  - Transmitter Channel-To-Channel Skew
    315
- Differential Pin Placement Guidelines
  320
Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices

333
Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

340
- Configuration Devices
  340
- Configuration Features
  342
- Power-On Reset Circuit
  343
- Fast Passive Parallel Configuration
  344
- JTAG Configuration
  373
  - Jam STAPL
    378
- Configuration Data Decompression
  386
- Remote System Upgrades
  388
  - Functional Description
    389
  - Enabling Remote Update
    391
  - Configuration Image Types
    392
- Dedicated Remote System Upgrade Circuitry
  395
  - Remote System Upgrade Registers
    396
    
    Remote System Upgrade Status Register
    397
  - Remote System Upgrade State Machine
    398
  - User Watchdog Timer
    400
- Quartus II Software Support
  401
- Design Security
  402
  - Stratix IV Security Protection
    403
  - Stratix IV Design Security Solution
    404
  - Security Modes Available
    405
    
    No Key Operation
    406
Chapter 11 .SEU Mitigation in Stratix IV Devices

410
- Error Detection Fundamentals
  410
  - Automated Single-Event Upset Detection
    413
- Error Detection Block
  414
  - Error Detection Registers
    415
- Error Detection Timing
  416
  - Software Support
    418
- Recovering from CRC Errors
  419
Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices

421
- BST Architecture
  421
- BST Operation Control
  422
- I/O Voltage Support in a JTAG Chain
  424
- Overview
  427
Chapter 13 .Power Management in Stratix IV Devices

428
- Stratix IV Power Technology
  428
- Stratix IV External Power Supply Requirements
  429
- Temperature Sensing Diode
  430
- About this Handbook
  433

Altera Stratix IV Using Manual (59 pages)

Using DDR3 SDRAM in Devices

Brand: Altera | Category: Motherboard | Size: 2.56 MB

Altera Categories

Motherboard Microcontrollers Computer Hardware Transceiver Media Converter

More Altera Manuals

Altera Stratix IV Manuals

Altera Stratix IV Device Handbook (1157 pages)

Table of Contents

Table of Contents

Chapter 4 .DSP Blocks in Stratix IV Devices

Chapter 5 .Clock Networks and Plls in Stratix IV Devices

Chapter 6 .I/O Features in Stratix IV Devices

Chapter 13 .Power Management in Stratix IV Devices

Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices

Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices

Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

Chapter 11 .SEU Mitigation in Stratix IV Devices

Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices

. Altgx_Reconfig Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration/Additional Information

Chapter 3. ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Dynamic Reconfiguration

Table of Contents

Chapter 1. DC and Switching Characteristics for Stratix IV Devices

Chapter 2. Addendum to the Stratix IV Device Handbook

Altera Stratix IV Handbook (434 pages)

Table of Contents

Chapter Revision Dates

Section I. Device Core

Chapter 1. Overview for the Stratix IV Device Family

Chapter 2 .Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices

Chapter 3. Trimatrix Embedded Memory Blocks in Stratix IV Devices

Chapter 4. DSP Blocks in Stratix IV Devices

Chapter 5 .Clock Networks and Plls in Stratix IV Devices

Chapter 6 .I/O Features in Stratix IV Devices

Chapter 8 .High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices

Chapter 9 .Hot Socketing and Power-On Reset in Stratix IV Devices

Chapter 10 .Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices

Chapter 11 .SEU Mitigation in Stratix IV Devices

Chapter 12 .JTAG Boundary-Scan Testing in Stratix IV Devices

Chapter 13 .Power Management in Stratix IV Devices

Altera Stratix IV Using Manual (59 pages)

Table of Contents

Related Products

Altera Categories