Altera Cyclone V User Manual page 92

6–4
Table 6–6
Table 6–6. Power Management Capability Structure, Rev2.1 Spec
Byte Offset
0x078 Capabilities Register
0x07C Data
Note to Table 6–6:
(1) Refer to Table 6–9 on page 6–5
Base Specification 2.0.
Table 6–7
Table 6–7. PCI Express Advanced Error Reporting Extended Capability Structure, Rev2.1 Spec: Advanced Error Reporting
Capability
Byte Offset
0x800 PCI Express Enhanced Capability Header
0x804 Uncorrectable Error Status Register
0x808 Uncorrectable Error Mask Register
0x80C Uncorrectable Error Severity Register
0x810 Correctable Error Status Register
0x814 Correctable Error Mask Register
0x818 Advanced Error Capabilities and Control Register
0x81C Header Log Register
0x82C Root Error Command
0x830 Root Error Status
0x834 Error Source Identification Register
Note to Table 6–7:
(1) Refer to Table 6–9 on page 6–5
Base Specification 2.0.
Table 6–8
Table 6–8. PCIe Capability Structure 2.1, Rev2.1 Spec (Part 1 of 2)
Byte Offset
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
Cyclone V Hard IP for PCI Express
describes the Power Management Capability structure.
31:24
PM Control/Status
Bridge Extensions
for a comprehensive list of correspondences between the Configuration Space registers and the
describes the PCI Express AER Extended Capability structure.
31:24
for a comprehensive list of correspondences between the Configuration Space registers and the
describes the PCI Express Capability Structure.
31:16
PCI Express Capabilities Register
Device Status
Link Status
Slot Status
Root Capabilities
23:16 15:8
Next Cap PTR
Power Management Status & Control
23:16 15:8
Correctable Error Source ID Register
15:8
Next Cap Pointer
Device Capabilities
Link
Slot
Root Status
Device Capabilities 2
Chapter 6: Register Descriptions
Configuration Space Register Content
7:0
Cap ID
PCI Express
7:0
PCI Express
7:0
PCI Express Cap ID
Device Control 2
Link Control
Slot Control
Root Control
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