Chapter 10. Interrupts; Interrupts For Endpoints; Msi Interrupts - Altera Cyclone V User Manual

November 2011
1101
This chapter describes interrupts for the following configurations:

Interrupts for Endpoints

■
■ Interrupts for Root Ports
Refer to
page 5–18
Interrupts for Endpoints
The Cyclone V Hard IP for PCI Express provides support for PCI Express legacy
interrupts, MSI, and MSI-X interrupts when configured in Endpoint mode. The MSI,
MSI-X, and legacy interrupts are mutually exclusive. After power up, the Hard IP block
starts in INTX mode, after which time software decides whether to switch to MSI
mode by programming the msi_enable bit of the MSI message control register
(bit[16] of 0x050) to 1 or to MSI-X mode if you turn on Implement MSI-X under the
PCI Express/PCI Capabilities tab using the parameter editor. If you turn on the
Implement MSI-X option, you should implement the MSI-X table structures at the
memory space pointed to by the BARs.
f
Refer to section 6.1 of
Express interrupt support for Endpoints.

MSI Interrupts

MSI interrupts are signaled on the PCI Express link using a single dword memory
write TLPs generated internally by the Cyclone V Hard IP for PCI Express. The
app_msi_req input port controls MSI interrupt generation. When the input port
asserts app_msi_req, it causes a MSI posted write TLP to be generated based on the
MSI configuration register values and the app_msi_tc and app_msi_num input ports.
Software uses configuration requests to program the MSI registers. To enable MSI
interrupts, software must first set the MSI enable bit
then disable legacy interrupts by setting the Interrupt Disable
page
Figure 10–1
Figure 10–1. MSI Handler Block
November 2011 Altera Corporation
"Interrupts for Endpoints" on page 5–17
for descriptions of the interrupt signals.
PCI Express 2.1 Base Specification
6–2) bit.
illustrates the architecture of the MSI handler block.
and "Interrupts for Root Ports" on
for a general description of PCI
(Table 5–15 on page
app_msi_req
app_msi_ack
MSI Handler
app_msi_tc
Block
app_msi_num
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
10. Interrupts
5–27) and
(Table 6–2 on
Cyclone V Hard IP for PCI Express