Altera Cyclone V User Manual page 86

Hard ip for pci express
Hide thumbs Also See for Cyclone V:
Table of Contents

Advertisement

5–34
Table 5–22. PIPE Interface Signals (Part 2 of 3)
Signal
(1)
txcompl0
(1)
rxpolarity0
(1)
powerdown0[1:0]
tx_deemph0
(1) (2)
rxdata0[15:0]
(1) (2)
rxdatak0[1:0]
(1) (2)
rxvalid0
(1) (2)
phystatus0
eidleinfersel0[2:0]
(1) (2)
rxelecidle0
(1) (2)
rxstatus0[2:0]
Cyclone V Hard IP for PCI Express
I/O
Transmit compliance <n>. This signal forces the running disparity to
O
negative in compliance mode (negative COM character).
Receive polarity <n>. This signal instructs the PHY layer to invert the
O
polarity of the 8B/10B receiver decoding block.
Power down <n>. This signal requests the PHY to change its power state
O
to the specified state (P0, P0s, P1, or P2).
Transmit de-emphasis selection. The Cyclone V Hard IP for PCI Express
sets the value for this signal based on the indication received from the
O
other end of the link during the Training Sequences (TS). You do not
need to change this value.
I
Receive data <n>. This bus receives data on lane <n>.
Receive data control <n>. This signal separates control and data
I
symbols.
Receive valid <n>. This symbol indicates symbol lock and valid data on
I
rxdata<n> and rxdatak<n>.
PHY status <n>. This signal communicates completion of several PHY
I
requests.
Electrical idle entry inference mechanism selection. The following
encodings are defined:
3'b0xx: Electrical Idle Inference not required in current LTSSM state
3'b100: Absence of COM/SKP Ordered Set the in 128 us window for
Gen1 or Gen2
O
3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval for
Gen1 or Gen2
3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and
16000 UI interval for Gen2
3'b111: Absence of Electrical idle exit in 128 us window for Gen1
Receive electrical idle <n>. This signal forces the receive output to
I
electrical idle.
Receive status <n>. This signal encodes receive status and error codes
I
for the receive data stream and receiver detection.
Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Description
November 2011 Altera Corporation

Advertisement

Table of Contents
loading

Table of Contents