Altera Cyclone V User Manual page 77

Chapter 5: IP Core Interfaces
Transaction Layer Configuration Space Signals
Table 5–14. Configuration Space Register Descriptions (Part 2 of 3)
Width
Register
cfg_slotcsr
cfg_linkcsr,
cfg_link2csr
cfg_prmcsr_func<n>
cfg_rootcsr
cfg_seccsr
cfg_secbus
cfg_subbus
cfg_io_bas
cfg_io_lim
cfg_np_bas
cfg_np_lim
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cfg_slotcsr[31:16] is the Slot Control and
cfg_slotcsr[15:0]is the Slot Status of the PCI Express
16 O
capability structure. This register is only available in Root Port
mode.
cfg_linkcsr[15:0]is the primary Link Control of the PCI
32 O
Express capability structure.
cfg_link2csr[31:16] is the secondary Link Status and
cfg_link2csr[15:0]is the secondary Link Control of the PCI
Express capability structure for Gen2 operation.
When tl_cfg_addr=2, tl_cfg_ctl returns the primary and
secondary Link Control registers, {cfg_linkcsr[15:0],
cfg_lin2csr[15:0]}, the primary Link Status register,
cfg_linkcsr[31:16], is available on tl_cfg_sts[46:31].
For Gen1 variants, the link bandwidth notification bit is always
set to 0.
Base/Primary Control and Status register for the PCI
16 O
Configuration Space.
Root Control and Status register of the PCI-Express capability.
8 O
This register is only available in Root Port mode.
Secondary bus Control and Status register of the PCI-Express
16 O
capability. This register is only available in Root Port mode.
8 O Secondary bus number. Available in Root Port mode.
8 O Subordinate bus number. Available in Root Port mode.
The upper 20 bits of the IO limit registers of the Type1
20 O Configuration Space. This register is only available in Root Port
mode.
The upper 20 bits of the IO limit registers of the Type1
20 O Configuration Space. This register is only available in Root Port
mode.
The upper 12 bits of the memory base register of the Type1
12 O Configuration Space. This register is only available in Root Port
mode.
The upper 12 bits of the memory limit register of the Type1
12 O Configuration Space. This register is only available in Root Port
mode.
Description
Cyclone V Hard IP for PCI Express
5–25
Register
Reference
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
Table 6–8 on
page 6–4
Table 6–2 on
page 6–2
0x004 (Type 0)
Table 6–3 on
page 6–2
0x004 (Type 1)
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
Table 6–3 on
page 6–2
0x01C
Table 6–3 on
page 6–2
0x018
Table 6–3 on
page 6–2
0x018
Table 6–3 on
page 6–2
0x01C
Table 6–8 on
page 6–4
0x01C
Table 3–7 on
page 3–8
EXP ROM
Table 3–7 on
page 3–8
EXP ROM
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