Altera Cyclone V User Manual page 91

Chapter 6: Register Descriptions
Configuration Space Register Content
Table 6–3. PCI Type 1 Configuration Space Header (Root Ports) (Part 2 of 2), Rev2.1 Spec: Type 1 Configuration Space
Header
Byte Offset
0x020
0x024
0x028
0x02C
0x030
0x034 Reserved
0x038 Expansion ROM Base Address
0x03C
Note to Table 6–3:
(1) Refer to Table 6–9 on page 6–5
Base Specification 2.0.
Table 6–4
Table 6–4. MSI Capability Structure, Rev2.1 Spec: MSI Capability Structures
(1)
Byte Offsets
0x050 Configuration MSI Control Status Register Field
0x054
0x058
0x05C
Note to Table 6–4:
(1) Specifies the byte offset within Cyclone V Hard IP for PCI Express IP core's address space.
(2) Refer to Table 6–9 on page 6–5
Base Specification 2.0.
Table 6–5
Table 6–5. MSI-X Capability Structure, Rev2.1 Spec: MSI-X Capability Structures
Byte Offset
0x068
0x06C
Note to Table 6–5:
(1) Refer to Table 6–9 on page 6–5
Base Specification 2.0.
November 2011 Altera Corporation
31:24 23:16
Memory Limit
Prefetchable Memory Limit
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
I/O Limit Upper 16 Bits
Bridge Control
for a comprehensive list of correspondences between the Configuration Space registers and the
describes the MSI Capability structure.
31:24 23:16
Message Control
Descriptions
Reserved
for a comprehensive list of correspondences between the Configuration Space registers and the
describes the MSI-X Capability structure.
31:24
Message Control
MSI-X Table Offset
for a comprehensive list of correspondences between the Configuration Space registers and the
15:8
Prefetchable Memory Base
I/O Base Upper 16 Bits
Interrupt Pin
15:8
Next Cap Ptr
Message Address
Message Upper Address
23:16 15:8
Next Cap Ptr
7:0
Memory Base
Capabilities
Pointer
Interrupt Line
PCI Express
7:0
Capability ID
Message Data
PCI Express
7:3 2:0
Capability ID
Pending
Bit Array
(PBA)
Offset
PCI Express
Cyclone V Hard IP for PCI Express
User Guide
6–3