Receive Buffer Reordering - Altera Cyclone V User Manual

8–4
■ For memory read and write request with addresses below 4 GBytes, requestors
must use the 32-bit format. The Transaction Layer interprets requests using the
64-bit format for addresses below 4 GBytes as an Unsupported Request and does
not send them to the Application Layer. If Error Messaging is enabled, an error
Message TLP is sent to the Root Port. Refer to
Layer" on page 12–3
forward to the Application Layer.
■ The Transaction Layer sends all memory and I/O requests, as well as completions
generated by the Application Layer and passed to the transmit interface, to the
PCI Express link.
■ The Hard IP can generate and transmit power management, interrupt, and error
signaling messages automatically under the control of dedicated signals.
Additionally, it can generate MSI requests under the control of the dedicated
signals.
■ In Root Port mode, the Application Layer can issue Type 0 or Type 1 Configuration
TLPs on the Avalon-ST TX bus.
■
■

Receive Buffer Reordering

The RX datapath implements a RX buffer reordering function that allows posted and
completion transactions to pass non-posted transactions (as allowed by PCI Express
ordering rules) when the Application Layer is unable to accept additional non-posted
transactions.
The Application Layer dynamically enables the RX buffer reordering by asserting the
rx_mask signal. The rx_mask signal blocks non-posted request transactions made to
the Application Layer interface so that only posted and completion transactions are
presented to the Application Layer.
Table 8–2. Transaction Ordering Rules
Row Pass Column Posted Request
Memory Write or
Spec
(10)
Memory Write or
N
Message
Y/N
Request
Cyclone V Hard IP for PCI Express
for a comprehensive list of TLPs the Hard IP does not
The Type 1 Configuration TLPs are sent downstream on the PCI Express link
toward the Endpoint that matches the Completer ID set in the transmit packet.
If the bus number of the Type 1 Configuration TLP matches the Subordinate
Bus Number register value in the Root Port Configuration Space, the TLP is
converted to a Type 0 TLP.
The Type 0 Configuration TLPs are only routed to the Configuration Space of
the Hard IP and are not sent downstream on the PCI Express link.
(1)– (9)
(Part 1 of 2)
Non Posted Request
Message Read Request
Request
Hard IP Spec Hard IP Spec
(11) (11)
N
Y
(12) (12)
N
Chapter 8: Transaction Layer Protocol (TLP) Details
"Errors Detected by the Transaction
Table 8–2 lists the transaction ordering rules.
I/O or Cfg Write
Read Completion
Request
Hard IP Spec
Y/N
Y Y Y
Y
Receive Buffer Reordering
Completion
I/O or Cfg Write
Completion
Hard IP Spec Hard IP
(11) (11) (11)
N Y/N N
(12) (12) (12)
N Y N
November 2011 Altera Corporation
(11)
(12)